Semiconductor memory mounted with cache memory

Details Semiconductor memory mounted with cache memory Semiconductor memory mounted with cache memory

2000-09-14

2001-09-11

Mai, Son (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S233100, C711S003000, C711S118000

Reexamination Certificate

active

06288923

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-260699, filed Sep. 14, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and, more specifically, to a high-speed circuit of a synchronous burst memory capable of performing an address pipeline operation, which is applied to a synchronous pipelined burst static random access memory (PBSRAM) and cache-mounted dynamic random access memory (DRAM).
In a prior art PBSRAM, an address is decoded in synchronization with a clock signal in read mode, a very small potential is read out of a memory cell selected by the decoded address and amplified through a sense amplifier, and data of the sense amplifier is transferred to an output register.
Addresses are generated in sequence based on an input address using a given method such as a linear method and an interleaving method. A series of data items (e.g., four data items) read out from a memory cell corresponding to a series of addresses is output from an output register.
The PBSRAM has the feature that the first access time period of the first access required until the first data read out of a memory cell of the first-designated address is output is longer than the second to fourth access time periods of the second to fourth accesses required until the second to fourth data read out of memory cells of the second address et seq.
FIG. 1
shows an example of timing of the prior art PBSRAM in read mode.
As shown in
FIG. 1
, the second to fourth access time periods each correspond to two clocks necessary for outputting data from the output register, whereas the first access time period requires extra time corresponding to clocks (the number of which is &agr;) necessary for decoding an address, amplifying a very small potential read out of a selected memory cell by the sense amplifier, and transferring data to the output register.
The number of clocks necessary for satisfying the first access is referred to as read latency. In the prior art PBSRAM, the read latency is long. Since the read latency is expressed by 2 clocks+&agr;, it is 4 when &agr; is 2.
The above-described prior art synchronous burst memory capable of performing an address pipeline operation cannot be increased in speed since the read latency is long.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed in order to resolve the above problem and its object is to provide a semiconductor memory which is suitably used as a high-speed cache memory and capable of improving the efficiency of use of a data bus by shortening the read latency in a synchronous burst memory capable of performing an address pipeline operation.
A semiconductor integrated circuit device according to the present invention, comprises a synchronous burst memory circuit section capable of performing an address pipeline operation, and a register array section constituting a cache memory in an address space of the synchronous burst memory circuit section, the register array section including a tag register array and a data register array, address signals, which are to be supplied to a memory cell array in the synchronous burst memory circuit section, being distributed to a tag address and a cache address of the tag register array, and the cache address is supplied to the data register array.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5226009 (1993-07-01), Arimoto
patent: 5586279 (1996-12-01), Pardo et al.
patent: 5845324 (1998-12-01), White et al.
patent: 6101146 (2000-08-01), Maesako et al.
patent: 6201724 (2001-03-01), Ishizaki et al.
MOS Memory (SRAM) Data Book of Toshiba, TC55V2377BFF-275-300, pp. 370-387, (Sep. 1999).

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