Semiconductor memory module

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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Details

C365S063000, C365S189050, C365S233100

Reexamination Certificate

active

07061784

ABSTRACT:
The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

REFERENCES:
patent: 5867448 (1999-02-01), Mann
patent: 6125419 (2000-09-01), Umemura et al.
patent: 6142830 (2000-11-01), Loeffler
patent: 6356502 (2002-03-01), Yi
patent: 6449213 (2002-09-01), Dodd et al.
patent: 6530006 (2003-03-01), Dodd et al.
patent: 2004/0105292 (2004-06-01), Matsui
patent: 1 069 509 (2001-01-01), None

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