Semiconductor memory module

Details Semiconductor memory module Semiconductor memory module

2003-01-14

2004-11-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

C365S201000, C365S189090

Reexamination Certificate

active

06826066

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory module wherein semiconductor chips are mounted on a module substrate.
2. Description of the Background Art
A semiconductor memory device is, in many cases, utilized in a personal computer, a workstation or the like. In addition, in recent personal computers speed has been increased, density has been increased and performance has been enhanced and, therefore, further increase in memory capacity of semiconductor memory modules is required. In addition, there is an expanding market demand for low cost memories. Therefore, a further increase in the capacity of, and a lowering in the cost of, semiconductor memory devices have come to be required.
The amount of utilization of DRAMs (Dynamic Random Access Memories) for personal computers and the like has increased from among the above described semiconductor memory devices because of the advantage from the point of view of cost per unit bit. Even in the case that the capacity of a DRAM is increased, the cost per unit bit can be reduced by increasing the diameter of wafer for DRAMs. Therefore, DRAMs are frequency utilized.
Even in the case of a DRAM, however, the test period of time and test cost accompanying the increase in capacity have increased and the development costs accompanying improvements in microscope processing technology and costs for increasingly sophisticated facilities have greatly increased and, therefore, the question arises of whether or not these costs can be reduced.
In general, there are three types of bit configurations, four bit, eight bit and sixteen bit, of the input/output of a DRAM, so that the number of types of bit configurations is small. Therefore, in general, one module made up of a plurality of DRAMs is utilized. Semiconductor memory devices such as DRAMs are, in many cases, utilized in module conditions, as described above.
FIGS. 25 and 26
show an example of a semiconductor memory module according to a prior art. The semiconductor memory module according to a prior art has a structure wherein a single chip
117
having a bare chip
101
, a die pad
104
, bonding wires
105
and a lead frame
110
sealed in mold resin
108
is mounted on a module substrate
102
, such as of an SOP (Small Outline Package) and of a TSOP (Thin Small Outline Package), corresponding to a surface mounting technology wherein parts can be mounted on both surfaces of a printed circuit board. In addition, data input/output terminals DQ
0
to DQ
63
, for inputting/outputting signals connected to lead frames
110
of single chips
117
, are provided on module substrate
102
.
In addition, a basic trend of developing thinner and more miniaturized memory packages has been progressing, together with the enhancement of performance and functions of memory chips. Thus, package modes have greatly changed such that in addition to the insertion system that has been previously adopted for memory packages, in recent years a surface mounting system has been adopted.
At present, the surface mounting system has become the main trend, as opposed to the insertion system, and further reduction in size and in weight of packages is greatly required. Simplification of design, increase in reliability and reduction in cost has been achieved up to the present by utilizing semiconductor memory modules.
In addition, in the case that a defective chip is discovered in a module test after the manufacture of a semiconductor memory module, testing and replacement of defective chips are repeatedly carried out until defects are no longer found in the manufacturing process of a semiconductor memory module according to a prior art.
In general, a DRAM is provided with an internal voltage generation circuit for generating a predetermined internal voltage utilizing a power supply voltage VDD supplied from the outside. The internal voltage generation circuit is, for example, a word line driving voltage VPP generation circuit, a reference voltage VREFD generation circuit for a VPP generation circuit, a sense amplifier power supply voltage VDDS generation circuit within a memory array, a reference voltage VREFS generation circuit for a VDDS generation circuit, a cell plate voltage VCP generation circuit, a bit line voltage VBL generation circuit, a substrate bias voltage VBB generation circuit or the like.
A method is used for controlling the above described internal voltage generation circuit by converting a DRAM to a variety of test modes for a short period of time in order to detect whether or not the DRAM is defective for tests at the time of delivery of the DRAM. According to this method, it becomes possible for a DRAM to forcefully apply a predetermined voltage to an internal circuit. Here, a predetermined voltage is generated in an internal voltage generation circuit by applying a voltage to the internal voltage generation circuit from the outside. This predetermined voltage generated in the internal voltage generation circuit is applied to the internal circuit. Hereinafter the expression “a voltage is forced” is used to indicate “a voltage is forcefully applied to an internal circuit.”
FIGS. 27
to
29
are diagrams for describing a semiconductor memory module according to a prior art, on which is mounted a synchronous DRAM (hereinafter referred to as “SDRAM”), which is an example of a single chip
117
, that can be converted to a test mode before it is mounted on a module substrate
102
so that a voltage generated by an internal voltage generation circuit is controlled.
In the following, a method for controlling an internal voltage generated by an internal voltage generation circuit of an SDRAM, from the outside of the SDRAM, before the SDRAM is mounted on module substrate
102
is described in reference to
FIGS. 27
to
29
.
FIG. 27
is a diagram shown an enlarged view of one single chip
117
from among a plurality of single chips
117
in the semiconductor memory module shown in FIG.
25
. Here, single chip
117
of
FIG. 27
is shown as a schematic sketch so that the structure within mold resin
108
can be seen. In addition, a lead frame
110
is electrically connected to bonding pads
106
via bonding wires
105
.
In addition,
FIG. 28
is a diagram schematically showing the internal structure of a bare chip
101
. A test mode detection circuit
150
, shown in
FIG. 28
, generates a control signal for controlling an internal voltage generation circuit and an internal voltage force circuit. The two-stage procedure shown in the following is required in order to enter into individual test modes in order to control the internal voltages generated by a variety internal voltage generation circuits.
First, as a first stage shown in
FIG. 29
, commands inputted to a chip selection terminal/CS, a row address strobe terminal/RAS, a column address strobe terminal/CAS and a write enabling terminal/WE, provided in a single chip
117
as shown in
FIG. 27
, are converted to mode register set (hereinafter referred to as “MRS”) commands, that is to say, /CS=L, /RAS=L, /CAS=L and /WE=L are attained. In addition, commands inputted to bank address selection signal input terminals BA
0
, BA
1
and an address signal input terminal A
7
are set at BA
0
=H, BA
1
=H and A
7
=H. Thereby, single chip
117
enters into a test mode.
After that, as a second stage, the above described MRS commands are again inputted to a chip selection terminal/CS provided in single chip
117
, to row address strobe terminal/RAS, to column address strobe terminal/CAS and to write enabling terminal/WE. Thereby, individual test modes determined in accordance with the types of commands inputted to band address selection signal input terminals BA
0
and BA
1
as well as to address signal input terminals A
0
to An are entered. Here, Table 1 shows types of commands for entering a variety of voltage force modes.
TABLE 1
TITLE OF TEST
MODE
COMMAND
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VREFD FORCE
MRS
L
H
—
—
—
—
—
H
L
H
L
H
H
H
H
MODE

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