Semiconductor memory module

Details Semiconductor memory module Semiconductor memory module

2002-11-04

2004-09-28

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

C365S063000, C365S200000

Reexamination Certificate

active

06798679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory module wherein semiconductor chips are mounted on a module substrate.
2. Description of the Background Art
A semiconductor memory device is, in many cases, utilized in a personal computer, a workstation or the like. In addition, in recent years the speed, degree of compactness and number of functions of personal computers have been increased and, therefore, semiconductor memory devices have been required to further increase their memory capacity. In addition, the market has expanded so that a large number of low-cost memory devices are used. Therefore, further increase in the capacity of and further reduction in costs of semiconductor memory devices have become required.
The number of DRAMs (Dynamic Random Access Memory), from among the above described semiconductor memory devices, utilized in personal computers or the like has increased because it is advantageous from the point of view of cost per unit bit. Cost per bit unit can be reduced by increasing the diameter of wafers even in the case that the capacity is increased and, therefore, DRAMs are frequently utilized.
In a DRAM, however, cost of development, cost for high level institutions and the like have greatly increased together with the increase in the testing period of time and test costs accompanying the increase in capacity as well as the enhancement of microscopic processing technology so that whether or not those costs can be reduced has become a problem.
The bit configuration for the input to or output from a DRAM is conventionally 4 bits, 8 bits or 16 bits. Accordingly, the variety in types of bit numbers of a DRAM is small. Therefore, one module is normally made up of a plurality of DRAMs for general utilization. Thus, a semiconductor memory device such as a DRAM is, in many cases, utilized in a module condition.
FIGS. 31 and 32
show a conventional semiconductor memory module. The conventional semiconductor memory module has a structure, wherein single chips
117
, in which bare chips
101
, mounting islands
104
, bonding wires
105
and lead frames
110
are molded into mold resins
108
, are mounted on a module substrate
102
, such as of an SOP (Small Outline Package) or a TSOP (Thin Small Outline Package) corresponding to a surface mounting technology wherein parts can be mounted on both sides of a printed circuit board.
In addition, development has progressed of a memory package having a basic tendency toward miniaturization and thinning together with enhancement of performance and of functions of a memory chip. Then, though an insertion system has been adopted for a memory package, in recent years the forms of packages have greatly changed such that a surface mounting system has started to be adopted.
At present, the surface mounting system has become the main trend in place of the insertion system and further miniaturization and lightening of a package are strongly required. Up to the present, simplification of design and increase in reliability, as well as reduction in cost, have been achieved by utilizing a semiconductor memory module.
In addition, in a conventional manufacturing process of a semiconductor memory module, in the case that a defective chip is discovered in a module test after the manufacture of a semiconductor memory module, testing and replacement of such a defective chip are carried out until such defect has been removed.
There is a problem wherein a great amount of time and effort are required for the above described replacement of a memory chip that has been detected as being defective according to the conventional manufacturing process of a semiconductor memory module. Though there is a memory module in the form of a COB (Chip On Board) as a semiconductor memory module for solving this problem, a bare chip that has been detected as being defective cannot be replaced with a new good bare chip after bare chips have been sealed into a mold according to the conventional module in the form of the COB. Therefore, there is a problem wherein the memory module in the form of the COB cannot be repaired after the bare chips have been sealed into the mold.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory module wherein, even in the case that a semiconductor chip is detected as being defective after semiconductor chips are mounted on a module substrate, semiconductor chips other than the semiconductor chip that has become defective from among the plurality of semiconductor chips are effectively utilized and the semiconductor chip that has become defective can be repaired by newly mounting a good function chip (nondefective chip; The chip function without any problem in usual use) without interfering with the functions of the semiconductor memory module.
In order to achieve the above described object, it is necessary to prevent the semiconductor chip that has been detected as being defective from interfering with the input/output of data to/from the good chip for repair when operating. Therefore, the semiconductor chip that has been detected as being defective must be converted to the deactivated condition. Then, the semiconductor memory modules according to the respective aspects of the present invention shown below allow the semiconductor chips to be converted to the deactivated condition. In the following, the semiconductor memory modules of the respective aspects of the present invention that can achieve the above described object will be described.
A semiconductor memory module of the first aspect of the present invention has the following structure. The semiconductor memory module has semiconductor chips mounted on a module substrate. In addition, data input/output parts are electrically connected to the semiconductor chips so that the data input/output parts input/output data to/from the semiconductor chips. In addition, the semiconductor memory module is provided with a deactivated condition signal input part that allows the input of a deactivated condition signal indicating conversion to the deactivated condition wherein data inputted from a data input/output part is not inputted to a data memory region of a semiconductor chip. In addition, a circuit for activation/deactivation control is provided within a semiconductor chip for carrying out conversion to the deactivated condition in the case that a deactivated condition signal is inputted from a deactivated condition signal input part. A plurality of units having data input/output parts, deactivated condition signal input parts and circuits for activation/deactivation control is mounted on the module substrate. The plurality of semiconductor chips includes a plurality of bare chips. In addition, the plurality of bare chips is integrally covered with a mold resin on the module substrate. In addition, the deactivated condition signal input parts are provided outside of the mold resin.
According to the above described configuration, the semiconductor chips can be converted to the deactivated condition by inputting a deactivated condition signal from the deactivated condition signal input parts after the semiconductor chips are mounted on the module substrate.
A semiconductor memory module of the second aspect of the present invention has the following structure. The semiconductor memory module has semiconductor chips mounted on a module substrate. A self-refresh determination circuit that determines whether or not self-refreshing is carried out and that outputs a first signal in the case that it has been determined to carry out self-refreshing is provided within a semiconductor chip. In addition, the semiconductor memory module is provided with a signal input part that allows the input of a second signal different from the first signal. Furthermore, a self-refresh signal output circuit for outputting a self-refresh signal indicating a semiconductor chip to be self-refreshed in at least one case among the cases where a first signal is inputted and where a second signal is inputted

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