Semiconductor memory integrated circuit

Details Semiconductor memory integrated circuit Semiconductor memory integrated circuit

1989-12-05

1991-11-12

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read only systems

Semiconductive

365185, 36523006, 36523008, 3072961, 307451, 307475, 307452, G11C 1708

Patent

active

050653610

ABSTRACT:
A semiconductor memory integrated circuit is made up of a decoder, a memory matrix, and a decode output buffer selectively receiving a first or second power source voltage. The decode output buffer is provided between the decoder and the memory matrix, and includes an inverter circuit for inverting the output signal of the decoder, and a MOS transistor of a depletion mode, the gate of which is connected to the output terminal of the inverter, the first end of which is connected to a supply node of the first or second power source voltage, and the second end of which is connected to a power voltage supply node of the inverter circuit.

REFERENCES:
patent: 4697101 (1987-09-01), Iwahashi et al.
patent: 4788457 (1988-11-01), Mashiko et al.
patent: 4916334 (1990-04-01), Minagawa et al.

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