Semiconductor memory having twisted bit line architecture

Details Semiconductor memory having twisted bit line architecture Semiconductor memory having twisted bit line architecture

2007-08-14

2007-08-14

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

Magnetic

C365S063000, C365S214000

Reexamination Certificate

active

11258922

ABSTRACT:
A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.

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Tsutomu Yoshihara, et al., “A Twisted Bit Line Technique for Multi-Mb DRAMs”, IEEE International Solid-State Circuits Conference, Session XVI: Dynamic Memory, Feb. 19, 1988, pp. 238-239.
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