Semiconductor memory having sub-select lines cross-connected...

Details Semiconductor memory having sub-select lines cross-connected... Semiconductor memory having sub-select lines cross-connected...

2000-03-31

2001-02-13

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S200000, C365S201000, C365S230060, C365S227000

Reexamination Certificate

active

06188597

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, particularly to a semiconductor memory, such as a synchronous dynamic random-access memory (to be referred to as SDRAM hereinafter), using a shift redundancy system and formed by arranging decoding circuits of adjacent select lines (word lines) in a mirror image for the purpose of scale down.
2. Description of the Related Art
To increase the capacity and speed and reduce the consumption power of a memory and to reduce the wiring pitch by scale down, the general approach is to use a hierarchical word line system in a semiconductor memory such as SDRAM. In this hierarchical word line system, word lines are constituted by main select lines (mwl) and sub-select lines (swl). One select line selected by a main decoder (mwldec) is connected to a sub-decoder (swdec) having address information inputs for decoding and the corresponding sub-select line outputs. This sub-decoder selects one sub-select line in accordance with input address information.
For example, when eight sub-select lines belong to one main select line in a hierarchical word line system, to select one of these eight sub-select lines (⅛ selection), the sub-decoder performs ⅛-decoding to select one sub-select line from a main select line selected by the main decoder. For this purpose, eight sub-decoders are prepared for one main select line. Commonly, to reduce the circuit pitch, these eight sub-decoders are divided into two groups. Four sub-decoders are arranged at each end of a cell array block, and four sub-select lines run from these sub-decoders at one end alternately to oppose four corresponding sub-select lines at the other end in an interdigitated pattern.
In this arrangement, to place four sub-decoders within the pitch of eight sub-select lines, some layout improvements are made; four sub-decoders are grouped as one set, and signals and a power supply are shared by two adjacent sets. This is so because the size of a semiconductor integrated circuit is an important factor that determines the size of the whole system, so a reduction of the chip size by sharing is desired. Also, the smaller the chip size is, the larger the number of chips fabricated from one wafer is. Hence, it is essential to reduce the chip size by improving the layout efficiency.
To reduce the chip size in the hierarchical word line system, a method is known by which adjacent decoding circuits or decoding circuit sets are arranged in a mirror image (mirror arrangement or symmetrical arrangement) so that at least some decoding circuits or decoding circuit sets of word lines for selecting memory cells are shared. That is, a sharable portion is formed in a pitch end portion of each decoding circuit or decoding circuit set, and decoders are constituted by turning them back at these sharable portions.
FIGS. 1A and 1B
are plan views for explaining the effect of space reduction by the mirror arrangement of decoding circuits.
FIG. 1A
shows a common shift arrangement, not a mirror arrangement, of adjacent decoding circuits.
FIG. 1B
shows a mirror arrangement of adjacent decoding circuits.
As shown in
FIG. 1B
, when two decoding circuits are mirror-arranged, the ground electrode (GND) can be shared by these decoding circuits. This can reduce the space in a direction perpendicular to word lines compared to the shift arrangement as shown in FIG.
1
A. In this example, the space of two decoders in the direction perpendicular to word lines is 3.2 &mgr;m in the shift arrangement, whereas this space can be reduced to 2.4 &mgr;m in the mirror arrangement. That is, a space reduction of 0.8 &mgr;m is achieved.
Semiconductor memories such as SDRAMs are mass-produced because of their characteristics as products, and it is necessary strictly to guarantee the quality of each individual product. To guarantee this quality, various tests and evaluations are conducted before the shipment of products. The time required for these tests and evaluations is an important factor for determining the fabrication cost.
In guaranteeing the quality of a semiconductor memory, a shift redundancy system is known as a method of remedying defectives occurring in memory cells or word lines. In this shift redundancy system, the address of a main select line or a sub-select line is shifted one bit to the higher or lower bit position from a defective portion. In this system, address information on a defective location to be subjected to redundancy processing is loaded upon start-up of a device. In accordance with this address information, the relationships between decoders and drivers of select lines are appropriately switched, so that the defective address portion is not selected. Accordingly, no redundancy determination is necessary from the subsequent access, so it is possible to increase the access speed and reduce the consumption power. This address information of a defective portion is previously stored in an internal ROM or the like of a memory. Even if a memory cell or the like has a defect, therefore, by redundancy processing, the memory can be operated normally, without selecting this defective memory cell.
This shift redundancy system will be described below with reference to
FIGS. 2
to
4
.
FIGS. 2
to
4
are enlarged plan views of a cell array portion and a sub-decoder portion. In
FIGS. 2
to
4
, not only sets of four sub-decoders but also sub-decoders in each set are mirror-arranged. Of an externally input row address, a lower address (3 bits) is used to select a sub-decoder, and an address higher than that is used to select a main decoder.
When the lower bit address is incremented from
0
, sub-select lines swl<
0
> to swl<
31
> juxtaposed from the upper end to the lower end of
FIG. 2
are sequentially selected as indicated by their numbers. Even when the externally given address is sequentially incremented, these select lines are not sequentially selected from the end as shown in FIG.
2
. This is so because adjacent sub-decoders are mirror-arranged, so the order of addresses on the device is inconsistent with the order of externally supplied addresses.
Sub-decoders on the right-hand side of the cell array in
FIG. 2
are laid out such that sub-decoders
51
to
54
selected by main select line <
0
> (mwl<
0
>) and sub-decoders
55
to
58
selected by a main select line <
1
> (mwl<
1
>) are mirror-arranged with respect to the boundary between the sub-decoders
54
and
55
.
Furthermore, of one set of the sub-decoders
51
to
54
selected by main select line <
0
> (mwl<
0
>), the sub-decoders
51
and
52
and the sub-decoders
53
and
54
are mirror-arranged with respect to the boundary between the sub-decoders
52
and
53
. Sub-decoders selected by the other main select lines <
1
> (mwl<
1
>) to <
3
> (mwl<
3
>) are similarly mirror-arranged.
Accordingly, the sub-decoder
58
placed symmetrically with the sub-decoder
51
with respect to the boundary between the sub-decoders
54
and
55
is composed of transistors having the same configuration as the sub-decoder
51
and is selected by the same address signal. This also holds true for pairs of the sub-decoders
52
and
57
,
53
and
56
, and
54
and
55
; these sub-decoders of each pair are symmetrically arranged with respect to the boundary and selected on the basis of the same address signal.
The sub-select lines connected to the sub-decoders located on the right-hand side of
FIG. 2
are selected in the order of swl<
0
>, sw
2
<
2
>, swl<
4
>, and swl<
6
> by supplying four address signals by selecting main select line <
0
>. After that, main select line <
1
> is selected to supply address signals in the same order. As a consequence, these sub-select lines are selected in the order as shown in FIG.
2
.
To test and evaluate a semiconductor memory, it is sometimes necessary to select sub-select lines regularly in a certain direction, in order to write data in the form of a

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