Semiconductor memory having multiple data I/O with bit aligned a

Details Semiconductor memory having multiple data I/O with bit aligned a Semiconductor memory having multiple data I/O with bit aligned a

1992-05-18

1994-10-18

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiplexing

36523006, 3652385, G11C 800

Patent

active

053574770

ABSTRACT:
A memory includes a memory cell array unit, a plurality of memory cell bit lines connected to the memory cell array unit, a plurality of column selecting gates, and a plurality of sub data lines connected to the memory cell bit lines via the column selecting gates. A column selector serves to select and make conductive members of the column selecting gates so that data can be transmitted between successive members of the memory cell bit lines and the sub data lines. The memory further includes N-bit main data lines, where N denotes a given natural number. In addition, the memory includes data line selecting gates. The sub data lines are connected to the main data lines via the data line selecting gates. A data line selector serves to select and make conductive members of the data line selecting gates so that data can be transmitted between N successive members of the sub data lines and the main data lines.

REFERENCES:
patent: 4599709 (1986-07-01), Clemons
patent: 4764901 (1988-08-01), Sakurai
patent: 4896301 (1990-01-01), Ogawa
patent: 4941129 (1990-07-01), Oshima et al.
patent: 5040152 (1991-08-01), Voss et al.
patent: 5173878 (1992-12-01), Sakui et al.

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