Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-02-16
2001-02-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230030, C365S189080, C365S190000, C365S051000, C365S063000
Reexamination Certificate
active
06188634
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor memory having memory banks that can be selected by assigned memory bank decoders.
It is known that memory cells in a semiconductor memory are disposed in a matrix-like manner, that is to say in rows and columns. Respective address decoders are provided for rows and columns and make it possible to select one of the rows or columns, respectively. The memory cells are usually activated in a row-by-row manner via word lines, by access transistors being turned on, via which transistors access is made in each case to a capacitor storing the information of the memory cell. In a column-by-column manner, the conduction path of the transistors is connected to bit lines via which the information of a memory cell can be read out after amplification by a sense amplifier. Access is effected in a corresponding manner when information to be stored is written to the memory cell.
In recent semiconductor memories having dynamic memory cells (DRAMs), the memory cell array has a bank architecture. A memory bank contains all those functional units that are necessary to execute a memory access independently. A memory bank is therefore assigned respective row and column address decoders, and also sense amplifiers and other functional units required for the operation of the semiconductor memory, e.g. timing circuits, redundancy circuits, etc. If appropriate, functional units of different memory banks can be utilized together, for example sense amplifiers or bit line decoders or column decoders.
A memory bank and the functional units assigned to it are activated by memory bank decoders. If a specific memory cell in a memory bank is to be accessed, the functional units assigned to the memory bank are changed over from a standby state to an activated state. This addressing is effected by an output signal, assigned to the memory bank, of the memory bank decoder. Each memory bank has a unique memory bank address assigned to it. If this address is applied to the memory bank decoder, the latter's output signal assigned to the memory bank is activated.
As the number of memory banks increases, the memory bank decoders are becoming more and more complex. For example, a DRAM with a storage capacity of 64 MB contains 16 memory banks, and a DRAM with 128 MB contains 32 memory banks. A single decoder respectively having 16 or 32 output signals for activating a respective memory bank is so complex and requires, on the chip carrying the integrated semiconductor memory, such a large area in the circuitry realization that the regularity of the chip geometry is disturbed.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory having memory banks which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the configuration complexity for the memory bank decoders is reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory, containing:
a number of memory banks, each including:
a memory cell array having a multiplicity of memory cells disposed in a matrix-like manner having rows and columns and defining a matrix of memory cells; and
an address decoder for selecting one of a row and a column of the matrix of memory cells;
means for feeding in an address containing a number of address bits for selecting one of the row and the column of one of the memory cells by addressing the address decoder;
memory bank decoders, including:
a first memory bank decoder connected to a first group of the memory banks, the first memory bank decoder having an input side, an output side and generating a first respective bank selection signal available at the output side for each memory bank of the first group of the memory banks, resulting in one of the memory banks of the first group of memory banks being selected by an activation of the first respective bank selection signal; and
a second memory bank decoder connected to a second group of the memory banks and having an axially mirror-symmetrical layout with respect to the first memory bank decoder, the second memory bank decoder having an input side, an output side and generating a second respective bank selection signal available at the output side for each memory bank of the second group of the memory banks, resulting in that one of the memory banks of the second group of the memory banks being selected by an activation of the second respective bank selection signal; and
a predecoder having a logic circuit, an input side and an output side, the predecoder generating on the output side first address signals and second address signals complementary to the first address signals, the first address signals and the second address signals being fed to the first memory bank decoder and the second memory bank decoder, respectfully, and the input side of the predecoder receiving a portion of the address bits.
In the case of the semiconductor memory according to the invention, the layout of the memory bank decoders assigned to different groups of the memory banks is configured to be axially mirror-symmetrical. A changeover is made between the memory bank decoders by a predecoder. Since one of the memory bank decoders addresses only a portion of all the memory banks of the semiconductor memory, the circuits for the realization thereof are manageable. As a result of the axial mirroring of the layout and the provision of the predecoder, the number of decodable memory banks is doubled based on one memory bank decoder. In an advantageous manner, the mutually mirror-symmetrical memory bank decoders can be disposed at an edge end of the memory banks to which the memory bank decoders are respectively assigned. In an expedient manner, the groups of memory banks that are addressed by a respective memory bank decoder are positioned in the direction of the corners of a rectangular semiconductor chip containing the semiconductor memory. The memory bank decoder lies opposite the inwardly directed ends of the memory banks. Only the predecoder and the output signals generated by the predecoder lie between the groups of memory banks.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory having memory banks, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5867445 (1999-02-01), Kirsch et al.
patent: 0422299A1 (1991-04-01), None
patent: 0493615A1 (1992-07-01), None
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
Tran Andrew Q.
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