Semiconductor memory having load transistor circuit

Details Semiconductor memory having load transistor circuit Semiconductor memory having load transistor circuit

1987-09-09

1991-09-17

Bowler, Alyssa H.

Static information storage and retrieval

Read only systems

Semiconductive

369185, 36918911, G11C 700, G11C 1140, G11C 11412, G11C 1602

Patent

active

050501240

ABSTRACT:
A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

REFERENCES:
patent: 4387444 (1983-06-01), Edwards
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ISSCC'78 Session IX: "Static and Non Volatile Memories" by Chan 2/16/78, pp. 106-107.
Frohman-Bentchkowsky, "A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory," IEEE Journal of Solid-State Circuits, vol. SC-6, No. 5, pp. 301-306, Oct. 1971.

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