Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
1999-11-09
2001-03-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S063000, C365S149000, C365S230030
Reexamination Certificate
active
06201724
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor memory, and more particularly to a semiconductor memory having a register array that can function as a cache.
BACKGROUND OF THE INVENTION
FIG. 3
sets forth a conventional semiconductor memory. The semiconductor memory arrangement of
FIG. 3
can be referred to as a virtual channel memory. The virtual channel memory is designated by the general reference character
300
and can include a number of dynamic random access memory (DRAM) cells arranged into a memory cell array
302
. Memory cell array
302
can include DRAM cells arranged in row and column directions.
The virtual channel memory
300
can also include a register array section
304
. A register array section
304
can include a number of registers arranged in row and column directions. The number of rows and/or columns can be a predetermined ratio of the number of rows and columns in the memory cell array
302
. A register array section
304
can have a “cache” function.
One skilled in the art would recognize that a cache can store a portion of the data stored in a memory cell array. Access to the cache can be faster than access to the memory cell array. Data read operations can access a cache. If the data is stored within, there is a cache “hit” and the data can be accessed from a register array section
304
. If the data is not stored within the cache there is a cache “miss.”
The memory cell array
302
and register array section
304
can be connected to each other by transfer buses TBT
1
-
1
to TBN
1
-i. Additional transfer buses TBT
2
-
1
to TBN
2
-i can be connected to the register array section
304
. A read/write bus RWBT and RWBN can be connected to transfer buses TBT
1
-
1
to TBN
1
-i and TBT
2
-
1
to TBN
2
-i.
Data values of the conventional virtual RAM of
FIG. 3
can be read in a number of different ways. One type of read operation is a “continuous” read operation. One skilled in the art would recognize that a continuous read operation can be a series of read operations that occur one after another. As just one example, a continuous read operation may include a number of read operations that access the same row address, but different column addresses. A continuous read operation can include a “miss” to the register array section
304
. In a conventional continuous read operation that results in a register array miss, read data from memory cell array
302
is temporarily transferred to register array section
304
by way of transfer buses TBT
1
-
1
to TBN
1
-i. The data may then be read from the register array section
304
by way of transfer buses TBT
2
-
1
to TBN
2
-i.
In another type of read operation, data may be read directly from the memory cell array
302
, and not through register array section
304
. In such a read operation, data may be read by way of transfer buses TBT
1
-
1
to TBN
1
-i to local read/write bus LRWBT and LRWBN.
Data values may also be written to the virtual channel memory
300
in different ways. Data within register array section
304
may be written into memory cell array
302
by way of transfer buses TBT
1
-
1
to TBN
1
-i. Data may also be written to memory cell array
302
without using register array section
304
. Data on a local read/write bus LRWBT and LRWBN may be written into memory cell array
302
by way of transfer buses TBT
1
-
1
to TBN
1
-i.
The above-described approach to a virtual channel memory can have drawbacks. In the case of a continuous read operation, resulting from a register miss, data read from memory cell array
302
is temporarily transferred to register array section
304
, and then read afterward from the register array section
304
. As a result, continuous read operations may take considerable time.
SUMMARY OF THE INVENTION
It is an object of present invention to provide a semiconductor memory, having a register array section with a cache function, that provides a reduced access time when a read operation results in a miss to the register array section.
According to the various embodiments, a semiconductor memory can include a memory cell array having a number of memory cells arranged in row and column directions and a register array section having a number of registers arrays arranged in row and column directions. The numbers of register arrays may be a predetermined ratio of the number of rows and columns of memory cells. The semiconductor memory may further include a number of first switches, second switches, and third switches. The first switches can be situated between the register arrays and a transfer bus that is connected to the memory cell array. The second switches can be situated between the register arrays and a read/write bus. The third switches can be situated between the second switches and the read/write bus. A local read/write bus can be connected to the read/write bus, and a bus connector, activated by a read/write signal, can connect the transfer bus to the local read/write bus.
According to another aspect of the embodiments, a semiconductor memory can include a memory cell array having a number of memory cells arranged in row and column directions and a register array section having a number of registers arrays arranged in row and column directions. The numbers of register arrays may be a predetermined ratio of the number of rows and columns of memory cells. The semiconductor memory may further include a number of first switches, second switches, and third switches. The first switches can be situated between the register arrays and a transfer bus that is connected to the memory cell array. The second switches can be situated between the register arrays and a read/write bus. The third switches can have one end connected to the read/write bus and another end commonly connected to the second switches of the same register array column. A local read/write bus can be connected to the read/write bus, and a bus connector, activated by a read/write signal, can connect the transfer bus to the local read/write bus.
In the various embodiments, if a bus connector within a virtual channel memory is activated, data in a memory cell array can be transferred to a read/write bus, not through a register array section, but through a local read/write bus. At the same time, if first and second switches are turned on, data in the memory cell array can be transferred to the register array section. In this way, in a continuous read, a virtual channel memory can selectively provide a path for reading data to the read/write bus, through a bus connector, and also to the register array section. Consequently, first accesses on register array section misses can be shortened.
According to another aspect of the embodiments, a semiconductor memory can include a memory cell array having a number of memory cells arranged into row and column directions and a register array section having a number of registers arranged into rows and columns. A first transfer bus may transfer read and write data between the memory cell array and the register array section. A second transfer bus may transfer read and write data between the register array section and a read/write bus. A local read/write bus may transfer read and write data between the first transfer bus and the read/write bus. The semiconductor memory may further include a control circuit. in a continuous read operation, the control circuit can transfer first read data from the memory cell array to the read/write bus through the first transfer bus and the local read/write bus. The control circuit may also transfer second read data from the memory cell array to the register array section through the first transfer bus.
In the above-described arrangement, when data is read from the memory cell array in a continuous read operation, the control circuit can transfer the first read data from the memory cell array to the read/write bus via the first transfer bus and local read/write bus, and at the same time, second read data from the memory cell array can be transferred to the register array section via the first transfer bus. Thus, in a
Ishizaki Tatsuya
Suzuki Misao
Yoshida Souichirou
Ho Hoal V.
NEC Corporation
Nelms David
Walker Darryl G.
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