Semiconductor memory having improved data bus arrangement

Details Semiconductor memory having improved data bus arrangement Semiconductor memory having improved data bus arrangement

1996-05-22

1998-09-22

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523008, 36518905, G11C 800, G11C 700

Patent

active

058124780

ABSTRACT:
A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In preferred embodiments, the number of buffer circuits in the semiconductor memory is less than or equal to the number of memory cell arrays.

REFERENCES:
patent: 5303192 (1994-04-01), Baba
patent: 5412613 (1995-05-01), Galbi et al.
patent: 5416741 (1995-05-01), Ohsawa
patent: 5444305 (1995-08-01), Matsui
patent: 5491664 (1996-02-01), Phelan
patent: 5499215 (1996-03-01), Hatta
patent: 5502675 (1996-03-01), Kohno et al.

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