Semiconductor memory having high speed and low power data read/w

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365203, 365233, G11C 700

Patent

active

055026842

ABSTRACT:
A semiconductor memory, particularly a sychronous DRAM which includes a bus driving circuit driving read/write buses to first and second potentials in a write operation, a data amplifier driving the read/write buses to third and fourth potentials in a read operation, and a precharge control circuit precharging the data read/write buses to a precharge level to a predetermined level after the write operation has completed.

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