Semiconductor memory having electrically erasable and...

Details Semiconductor memory having electrically erasable and... Semiconductor memory having electrically erasable and...

2005-05-10

2005-05-10

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189070

Reexamination Certificate

active

06891759

ABSTRACT:
A method of operating an electrically alterable non-volatile multi-level memory device includes settling a status of at least one of the memory cell to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

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Bauer et al., “TA 7.7: A multi-level-cell 32Mb flash memory”, ISSCC95/Feb. 16, 1995/Digest of Technical Papers: Session 7, INTEL.

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