Semiconductor memory having electrically erasable and...

Details Semiconductor memory having electrically erasable and... Semiconductor memory having electrically erasable and...

2011-02-01

2011-02-01

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185030, C365S185210, C365S185290, C365S185240, C365S185200

Reexamination Certificate

active

07881111

ABSTRACT:
An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

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Bauer et al., “TA 7.7: A multi-level-cell 32Mb flash memory”, ISSCC95/Feb. 16, 1995/Digest of Technical Papers: Session 7, Intel Corp., pp. 132-133.

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