Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2010-06-09
2011-10-11
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S228000
Reexamination Certificate
active
08036033
ABSTRACT:
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.
REFERENCES:
patent: 4300212 (1981-11-01), Simko
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 5519831 (1996-05-01), Holzhammer
patent: 6141248 (2000-10-01), Forbes et al.
patent: 6163048 (2000-12-01), Hirose et al.
patent: 6166407 (2000-12-01), Ohta
patent: 6376876 (2002-04-01), Shin et al.
patent: 6614684 (2003-09-01), Shukuri et al.
patent: 6724657 (2004-04-01), Shukuri
patent: 6791882 (2004-09-01), Seki et al.
patent: 6801452 (2004-10-01), Miwa et al.
patent: 6954377 (2005-10-01), Choi et al.
patent: 7085156 (2006-08-01), Rerrant et al.
patent: 7118986 (2006-10-01), Steigerwalt et al.
patent: 2005/0024968 (2005-02-01), Lee et al.
patent: 2006/0125010 (2006-06-01), Bhattacharyya
patent: 2008/0123418 (2008-05-01), Widjaja
patent: 2009/0108351 (2009-04-01), Yang et al.
patent: 2009/0109750 (2009-04-01), Widjaja
patent: 2009/0190402 (2009-07-01), Hsu et al.
patent: 2010/0008139 (2010-01-01), Bae
Han et al. Programming/Erasing Characteristics of 45 nm NOR-Type Flash Memory Based on SOI FinFET Structure. vol. 47, Nov. 2005, pp. S564-S567.
Headland. Hot electron injection, Feb. 19, 2004.
Okhonin et al. A SOI Capacitor-less 1T-DRAM Concept. 2001, pp. 153-154.
Ranica et al. Scaled 1T-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications. Pascale.mazoyer@st.com, 2004, pp. 128-129.
Nguyen Tuan T.
Z End Semiconductor, Inc.
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