Semiconductor memory having an overlaid bus structure

Details Semiconductor memory having an overlaid bus structure Semiconductor memory having an overlaid bus structure

1997-03-11

1999-11-02

Hoang, Huan

Static information storage and retrieval

Addressing

Plural blocks or banks

365205, 365207, 365 63, G11C 800

Patent

active

059783001

ABSTRACT:
A plurality of sense amplifiers are provided between a plurality of memory cell arrays having a plurality of memory cells. These sense amplifiers are connected to bit lines of the respective memory cell arrays by array selection switches. Each of the sense amplifiers is connected to data lines by column switches. An array control portion is provided at each of the memory cell arrays. This array control portion selectively controls the array selection switches and column switches to transmit the data in an arbitrary memory cell in a memory cell array to the data lines through the sense amplifier.

REFERENCES:
patent: 5619473 (1997-04-01), Hotta
patent: 5621695 (1997-04-01), Tran
patent: 5671188 (1997-09-01), Patel et al.
Austrian Patent Office Service and Information Sector, Search Report and Examination Report, Dec. 18, 1998.

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