Semiconductor memory having a pulse generator for generating...

Details Semiconductor memory having a pulse generator for generating... Semiconductor memory having a pulse generator for generating...

2005-11-08

2005-11-08

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Addressing

Counting

C365S233100, C365S226000, C365S227000

Reexamination Certificate

active

06963518

ABSTRACT:
A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.

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