Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2000-11-09
2002-10-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S063000, C365S230030
Reexamination Certificate
active
06473327
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory such as a read only memory, and more specifically to such a semiconductor memory configured to have an elevated reading speed.
Conventionally, a mask ROM (read only memory) is used as one type of semiconductor memory. This mask ROM includes a synchronous ROM operating in synchronism with a supplied clock signal,
A typical synchronous mask ROM comprises a number of memory cells having a flat cell structure, arranged to constitute a NOR type cell array. In this NOR type cell array, a plurality of word lines are arranged to extend in a row direction (X-direction) so that memory cells included in one row are connected to a corresponding word line, and a plurality of bit lines are arranged to extend in a column direction (Y-direction) so that memory cells included in one column are connected to a corresponding bit line. The bit lines are paired, and each pair of bit lines are connected through an interconnection section to one digit line, which is connected to a sense amplifier and precharge circuit. In addition, a plurality of bank selection lines are located orthogonally to the bit lines to on-off control a transistor which is located in the interconnection section and is connected between each bit line and a corresponding digit line.
An X-decoder for the NOR type cell array fetches an address in response to a RAS (row address strobe) signal, and one bank select driver is connected to the X-decoder. A Y-decoder for the NOR type cell array fetches an address in response to a CAS (column address strobe) signal.
In the above mentioned synchronous mask ROM of the NOR type, 13 bits are allocated for a RAS address, and the number of bits of a CAS address is determined by the memory capacity of the NOR type cell array.
In addition, the word lines and the bank selection lines are formed of polysilicon, and the digit lines are formed of aluminum. Therefore, a signal propagation speed on the word lines and the bank selection lines is slower than a speed for selecting the digit line. In the prior art, therefore, an address for selecting the word line and the bank select line are allocated to the RAS address.
However, since the number of bits for the RAS address is as small as 13, the address is insufficient, and therefore, it was necessary to allocate the bank select lines for the CAS address. In this case, the speed for fetching the address in response to the CAS signal is determined by a bank selector.
Furthermore, in the synchronous mask ROM of the NOR type so configured that an X address is fetched in response to the RAS signal and a Y address is fetched in response to the CAS signal, one problem in speeding up is how fast the digit lines and the bit lines are precharged.
Therefore, it may be considered to elevate the performance of the precharge circuits for precharging the digit lines and the bit lines. However, the elevation of the performance of the precharge circuits causes another problem in which a current becomes too large or a current flowing out of the sense amplifier becomes too small, with the result that a delicate attention must be paid for adjustment of the precharge circuit.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor memory having an increased data reading speed.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor memory comprising:
a memory cell array including a number of memory cells arranged in a matrix having a plurality of rows and a plurality of columns;
a plurality of word lines each connected to a plurality of memory cells of a corresponding row of the plurality of rows in the memory cell array;
a plurality of bit lines each connected to a plurality of memory cells of a corresponding column of the plurality of columns in the memory cell array;
a row address decoder fetching an address in response to a row address strobe signal to decode the fetched address and to select one word lines from the plurality of word lines;
a column address decoder fetching the address in response to a column address strobe signal to decode the fetched address;
a column selection switch receiving the decoded address from the column address decoder for selecting one bit line from the plurality of bit lines;
a sense amplifier for precharging the bit line of a memory cell selected by the row address decoder and the column address decoder;
a precharge circuit for precharging the bit line of a non-selected memory cell; and
a pair of bank select drivers fetching the address in response to the column address strobe signal for raising up a bank select line for turning on a switch between the bit lines and a digit line, the pair of bank select drivers being located at opposite end sides of the bank select line, respectively.
With this arrangement, in response to the row address strobe signal, the row address decoder fetches the address to decode the fetched address and to select and activate one word line from the plurality of word lines. Then, in response to the column address strobe signal, the column address decoder fetches the address to decode the fetched address and to select one bit line from the plurality of bit lines by use of the column selection switch. Thus, one memory cell is selected by the given address. Furthermore, the address is fetched in response to the column address strobe signal, so that the bank select drivers located at the opposite end sides of the bank select line selected in accordance with the address are driven to activate or rise up the selected bank select line. Thus, a current flows from the sense amplifier through the bit line to the selected memory cell, so that the bit line of the selected memory cell is precharged. In addition, a current flows from the precharge circuit through the bit line to the selected memory cell, so that a non-selected bit line is precharged. Accordingly, the bit lines having a large capacitance is further quickly or surely precharged, with the result that the data reading operation from the fetching of the address to a data latching of an output stage can be quickened.
In one embodiment of the semiconductor memory, one of the pair of bank select drivers is located at a row address decoder side of the memory cell array, and the other of the pair of bank select drivers is located at a side of the memory cell array opposite to the row address decoder side.
Preferably, the semiconductor memory can further include a reference cell having the same structure as that of the memory cells and connected to the sense amplifier for supplying a reference voltage used for discriminating which of a high level and a low level an output of the selected memory cell is.
In a specific embodiment of the semiconductor memory, the memory cell array is of the NOR type. More specifically, the memory cells are of a flat cell structure.
In addition, the sense amplifier can receive an equalizing signal for changing over the sense amplifier between an activated condition and a deactivated condition.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.
REFERENCES:
patent: 5349563 (1994-09-01), Iwase
patent: 5886937 (1999-03-01), Jang
patent: 5909405 (1999-06-01), Lee et al.
patent: 6069831 (2000-05-01), Jang et al.
patent: 6072734 (2000-06-01), Choi
patent: 6088277 (2000-07-01), Kim et al.
Auduong Gene N.
NEC Corporation
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