Semiconductor memory for logic-hybrid memory

Details Semiconductor memory for logic-hybrid memory Semiconductor memory for logic-hybrid memory

2000-01-03

2002-04-09

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S226000, C365S203000, C365S189080

Reexamination Certificate

active

06370080

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a dynamic RAM used in semiconductor memory systems.
2. Background of the Invention
In recent years, the width of circuits in semiconductor devices has decreased. This reduction in circuit width has increased the capacity of semiconductor memory. As memory capacity increases, the memory is referred to as large scaled. As memory size increases, memory efficiency is a desired quality. Logic-hybrid memory includes a logic block that functions beyond merely controlling reading and writing to specific memory cells. Logic blocks also control a signal called an I/F signal that performs an interface (I/F) between the logic block and the memory block.
An example of this type of semiconductor where the semiconductor chip includes a logic circuit and a memory is described in “A 500-Megabyte
Data-Rate 4.5M DRAM” Kushiyama et al.,
IEEE Journal of Solid
-
State Circuits
Vol. 28, No. 4, April 1993. This article illustrates in
FIGS. 4 and 10
and describes a memory block (DRAM CORE) and a logic block (INTERFACE LOGIC) in a chip. Signals, such as /RAS, /CAS, and an address signal are control signals from the exterior of the chip, or in a conventional memory chip are the interface (I/F) signals sent between the logic block and the memory block. The I/F signals are basic signals for control of the logic block and operations of the memory block.
Usually, the logic block controls the I/F signal so that the memory block can operate normally. However, problems occur when the logic block does not operate normally. This may be due to abnormal signals generated by the logic block operating in an unstable state. Often these unstable states occur immediately after power is turned on. Other events causing abnormal signals are temporary, unexpected wave forms from the logic block due to various external factors, such as a changing power source or a change in temperature during a burn-in examination.
When memory block receives an abnormal signal, dangerous, large currents can be generated damaging the internal circuit of the memory block. This event may cause latch up and can fatally damage the semiconductor package or circuit board. If the memory block is not initialized correctly, the reading and writing operations normally performed when the power source is turned on cannot be performed. The problem of conventional logic-hybrid memory is the logic block and the memory block are connected to each other only through the I/F signal. No mechanism protects the memory block against abnormal signals generated by the logic block.
SUMMARY OF THE INVENTION
This invention provides semiconductor protection for memory that is susceptible to abnormal and damaging signals from the logic block. An object of the invention is the interruption of abnormal signals from the logic block. This is accomplished by the semiconductor memory having a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control system cutting off the first control signal line in case a predetermined number of control signals are abnormal, and a second voltage control system cutting off the second control signal line in case a predetermined number of control signals are abnormal, preventing these abnormal signals from reaching the memory cell array.


REFERENCES:
patent: 5036227 (1991-07-01), Jo et al.
patent: 5311467 (1994-05-01), Lysinger et al.
patent: 5379261 (1995-01-01), Jones, Jr.
patent: 5559753 (1996-09-01), Kocis
patent: 5583816 (1996-12-01), McClure
patent: 5661683 (1997-08-01), Song
patent: 5751645 (1998-05-01), Tsukikawa
patent: 5875148 (1999-02-01), Tanaka et al.
patent: 5892726 (1999-04-01), Moon et al.
patent: 5896336 (1999-04-01), McClure
patent: 5-334879 (1993-12-01), None
patent: 93-8862 (1993-05-01), None
patent: 95-4517 (1995-02-01), None
A 500-Megabyte/s Data-Rate 4.5M DRAM, N. Kushiyama, S. Ohshima, D. Stark, H. Noji, K. Sakurai, S. Taklase, T. Furuyama, R.M. Barth, A. Chan, J. Dillon, J.A. Gasbarro, M.M. Griffin, M. Horowitz, T.H. Lee and Victor Lee, IEEE Journal of Solid State Circuits, vol. 28, No. 4, Apr. 1993.

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