Semiconductor memory equipped with row address decoder...

Details Semiconductor memory equipped with row address decoder... Semiconductor memory equipped with row address decoder...

2000-10-13

2001-06-05

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189080

Reexamination Certificate

active

06243319

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory, more particularly, to a semiconductor memory equipped with a row address decoder having a reduced signal propagation delay time.
2. Description of the Related Art
In a semiconductor memory, a row address is decoded by a decoder circuit to activate a single word line in a memory cell array.
FIG. 13
shows a decoder circuit for decoding a 2-bit row address with four 2-input NAND gates.
In this circuit scheme, 2
N
N-input NAND gates are required in a case of an N-bit row address . The N-input NAND gates having 2
N
outputs are disposed beside a memory cell array in order to decrease a total length of all interconnecting lines. However, when a value N is larger, the size of N-input NAND gate circuit increases, therefore the row pitch of memory cell is so larger that the memory density of the memory cell decreases.
Hence, a row address decoder circuit has been made to have a two stage configuration divided into a pre-decoder on the row address input side and a main decoder on the memory cell array side.
FIG. 14
shows a prior art 4-bit row address decoder circuit.
The pre-decoder
10
consists of a 2-bit decoder
11
for lower 2 bits A
1
and A
0
and a 2-bit decoder
12
for higher 2 bits A
3
and A
2
. One of 4 outputs from the 2-bit decoder
11
and one of 4 outputs from the 2-bit decoder
12
are combined and all the combinations are provided to individual 2-input NAND gates in a main decoder
20
.
The number of row address bits increases with increase in a storage capacity of a semiconductor memory, leading to a larger length of interconnecting lines between the pre-decoder
10
and the main decoder
20
. Generally speaking, when a row address increases by one bit, the average length of interconnection lines between a pre-decoder and a main decoder increases to be twofold. When the length of interconnection line becomes twofold, each of a resistance value and a capacitance value thereof becomes twofold, causing a CR delay to be fourfold, with the result that rising and falling edge of a signal become gentle. Hence, an access time in a semiconductor memory increases to hinder a high-speed operation thereof.
FIG. 15
is a layout sketch of circuit blocks in a prior art semiconductor chip.
An address control circuit
30
includes an address buffer circuit, an address buffer register, and the pre-decoder, for receiving an address and providing a predecoded signal. The main decoder
20
provides a row select signal onto a word line of memory cell arrays MC
1
to MC
4
.
Contents of memory cells connected to an activated word line in the memory cell arrays MC
1
to MC
4
are provided to a data I/O control circuit
33
or
34
through bit lines. Each of the data I/O control circuits
33
and
34
includes sense amplifiers amplifying signals on bit lines, and column switches selecting an amplified signal according to a column address.
In order to achieve a fast operation with reducing a propagation delay time, in the prior art, such a configuration as
FIG. 16
was adopted. In
FIG. 16
, the address control circuit
30
of
FIG. 15
is divided into address control circuits
30
A and
30
B, and an address control circuit
30
A and a main decoder
20
A are provided for the memory cell arrays MC
1
and MC
2
, an address control circuit
30
B and a main decoder
20
B are provided for the memory cell arrays MC
3
and MC
4
, and data I/O control circuits
33
A,
34
A,
33
B and
34
B are provided for the memory cell arrays MC
1
, MC
2
, MC
3
and MC
4
, respectively.
However, there is an increase in the chip area of the semiconductor memory, resulting in higher cost compared with the configuration of FIG.
15
.
This problem is solved by adopting a configuration shown in
FIG. 17
in which the address control circuit
30
is disposed in a central portion, the data I/O control circuit
33
is disposed between the memory cell arrays MC
1
and MC
3
, and the data I/O control circuit
34
is disposed between the memory cell arrays MC
2
and MC
4
.
However, when the memory cell arrays MC
1
to MC
4
each become longer in a bit line direction in order to increase a storage capacity, the same problem as that of
FIG. 15
arises. Moreover, when the data I/O control circuits are distributed as shown in
FIG. 16
in order to solve the same problem as that of
FIG. 15
, the same problem as that of
FIG. 16
then arises.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory equipped with an address decoder circuit capable of reducing a decoding time without increasing in chip area.
In one aspect of the present invention, there is provided a semiconductor memory comprising a first memory cell array, having first word lines; a second memory cell array, arranged adjacent to the first memory cell array in a direction perpendicular to the first word lines, having second word lines; a pre-decoder, predecoding an address signal to provide a first predecoded signal; a first main decoder, further decoding the first predecoded signal to provide a first decoded signal to the first word lines; an inverting circuit, inverting a logic level of the first predecoded signal to generate a second predecoded signal; and a second main decoder, further decoding the second predecoded signal to provide a second decoded signal to the second word lines.
The term “memory” includes a memory circuit in a semiconductor device such as a MPU, a DSP or a memory device.
With this aspect, sum of CR values of interconnecting lines between a pre-decoder and a second main decoder is reduced, signal edges become steeper and the signal propagation delay time in the row decoder circuit is reduced, with the result that an access time in the semiconductor memory can be shorter.
Further, since the number of gate stages of the inverting circuit can be one, a chip area can be smaller than a case where a non-inverting circuit with two gate stages is adopted instead of the inverting circuit.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 5047983 (1991-09-01), Iwai et al.
patent: 5610874 (1997-03-01), Park et al.
patent: 5889725 (1999-03-01), Aikawa et al.
patent: 6055203 (2000-04-01), Agarwal et al.

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