Semiconductor memory employing a block-write system

Details Semiconductor memory employing a block-write system Semiconductor memory employing a block-write system

1996-08-02

1997-08-05

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, G11C 804

Patent

active

056549342

ABSTRACT:
A semiconductor memory comprises a memory cell array having bit line pairs, a pair of I/O lines, column switches connected between the pair of I/O lines and an associated one of the bit line pairs, a timing signal generator generating a timing signal, an address latch circuit latching an address signal in response to the timing signal and a column decoder decoding the address signal latched into the address latch circuit to activate at least one of the column switches. The timing signal generator generates the timing signal synchronized with a clock signal during the normal write operation, and generates the timing signal having a lower frequency than the clock signal during the block-write operation.

REFERENCES:
patent: 5202857 (1993-04-01), Yanaz et al.
patent: 5539696 (1996-07-01), Patel
Samsung Electronics, Rev. 3, Aug. 1995, pp. 15-18.

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