Semiconductor memory driven at low voltage

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36518909, 36518911, G11C 800

Patent

active

054167477

ABSTRACT:
The signal levels of a plurality of word lines (high and low) are controlled by outputs of upper address decoders and a lower address decoder. Each of the upper address decoders, when it is selected, supplies a word line control signal from the lower address decoder to all the word lines. The word line control signal is used to supply a high voltage only to one word line and a ground potential to other word lines. On the other hand, when the upper address decoder is not selected, it supplies a nonselection level voltage from a low voltage generator. This voltage is lower than the ground potential. Thus, the voltage is applied to the gates of transfer gates connected to the word lines, thereby suppressing a subthreshold current to a small value, thereby decreasing a leakage current from memory cells.

REFERENCES:
patent: 5051959 (1991-09-01), Nakano et al.
patent: 5119334 (1992-06-01), Fujii
patent: 5257238 (1993-10-01), Lee et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor memory driven at low voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory driven at low voltage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory driven at low voltage will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-643437

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.