Semiconductor memory driven at low voltage

Details Semiconductor memory driven at low voltage Semiconductor memory driven at low voltage

1993-07-12

1995-05-16

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518909, 36518911, G11C 800

Patent

active

054167477

ABSTRACT:
The signal levels of a plurality of word lines (high and low) are controlled by outputs of upper address decoders and a lower address decoder. Each of the upper address decoders, when it is selected, supplies a word line control signal from the lower address decoder to all the word lines. The word line control signal is used to supply a high voltage only to one word line and a ground potential to other word lines. On the other hand, when the upper address decoder is not selected, it supplies a nonselection level voltage from a low voltage generator. This voltage is lower than the ground potential. Thus, the voltage is applied to the gates of transfer gates connected to the word lines, thereby suppressing a subthreshold current to a small value, thereby decreasing a leakage current from memory cells.

REFERENCES:
patent: 5051959 (1991-09-01), Nakano et al.
patent: 5119334 (1992-06-01), Fujii
patent: 5257238 (1993-10-01), Lee et al.

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