Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-07-11
2006-07-11
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S190000, C365S230060
Reexamination Certificate
active
07075854
ABSTRACT:
A semiconductor memory device and a write control circuit which may detect write failures and a write control method for the same are provided. The semiconductor memory device may include a memory cell array, a bit line amplifier, a switch unit, and a write driver. Exemplary embodiments of the semiconductor memory device, according to the present invention, may determine the activation timing of the column select line signal using a clock enable signal and a mode register set signal, without synchronizing with a master clock signal.
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Kang Sang-Seok
Lee Sei-Hui
Harness & Dickey & Pierce P.L.C.
Nguyen Tan T.
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