Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-02-20
2007-02-20
Tran, Michael (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S191000
Reexamination Certificate
active
10994632
ABSTRACT:
A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.
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Hara Kota
Yamada Shin-ichi
Arent Fox PLLC.
Fujitsu Limited
Tran Michael
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