Semiconductor memory device with wirings having ensured cross-se

Details Semiconductor memory device with wirings having ensured cross-se Semiconductor memory device with wirings having ensured cross-se

1988-06-06

1989-02-21

Edlow, Martin H.

357 41, 357 45, 357 59, 357 71, H01L 2348, H01L 2702, H01L 2710, H01L 2904

Patent

active

048070173

ABSTRACT:
In a memory cell matrix region of a semiconductor memory device such as a dynamic RAM or a static RAM, wirings of the same material are distributed between different layers in such a manner that the upper wirings overlap the lower wirings. Accordingly, the width of the wirings can be increased for a semiconductor memory device having a high concentration and high integration.

REFERENCES:
patent: 3946421 (1976-03-01), Hartsell et al.
patent: 4001871 (1977-01-01), Tsunemitsu
patent: 4206471 (1980-06-01), Hoffmann et al.
patent: 4328563 (1982-05-01), Schroeder
patent: 4536941 (1985-08-01), Kuo et al.
Terman, L. M. "Aluminum-Silicon Self-Aligned Gate 1-Device Cell with Narrow Word Line Pitch" IBM Technical Disclosure Bulletin, vol. 15, No. 4, Sep. 1972, pp. 1163-1164.

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