Semiconductor memory device with two layers of bit lines

Details Semiconductor memory device with two layers of bit lines Semiconductor memory device with two layers of bit lines

2001-01-26

2001-09-25

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S072000, C365S210130, C365S208000, C365S190000, C365S156000

Reexamination Certificate

active

06295222

ABSTRACT:

BACKGROUND OF THE INVENTION
1) Technical field of the Invention
The present invention relates to a semiconductor memory device including two layers of bit lines formed thereon.
2) Description of Related Arts
Semiconductor memory devices used in the recent office automation equipments, for example, a personal computer and a word processor, demand the semiconductor memory devices capable of storing and reading larger amount of data. In order to meet this demand, a variety of approaches have been proposed up to the present. Among others, commonly assigned U.S. Pat. Nos. 5,280,441 and 5,379,820 both granted to Wada et al. disclose a circuit design with a T-shaped bit line for connection between the memory device and circuits arranged therearound, which decreases limitations on the circuit and allows the circuits to be arranged in a suitable manner around the memory device. Also, commonly assigned U.S. Pat. Nos. 5,563,820 and 5,699,308 both granted to Wada et al. teach an integrated semiconductor memory device, of which high density is achieved by appropriately adjusting intervals between the adjacent first-layer bit lines. The aforementioned U.S. patents are incorporated herein by reference in this patent application.
When the integration of MOSFETs formed beneath the first-layer bit line is greater than that of metal wire layers, it is expected that the dimensions of memory cell regions may be subject to those of the dimensions of the first-layer and second-layer bit lines.
In particular, when the through-hole acting as a connecting hole between the first-layer and second-layer bit lines is arranged on a memory cell region, the interval of adjacent first-layer bit lines are extended so that the dimension of the memory cell region should also be extended. Thus, the dimension of a memory cell arrays is extended, and the area thereof is increased. In other words, this causes the enlargement of the memory cell array, preventing the array from being highly integrated.
Details of prior arts and defects thereof are also described in the description of the Japanese Patent Application No. 11-347449, filed by the applicant.
SUMMARY OF THE INVENTION
The present invention is to address to the aforementioned problem, and an object thereof is to prevent the dimensions of memory cell array from being extended due to an existence of the connecting holes even where the dimension of memory cell regions may be determined by those of first-layer and second-layer bit lines.
The semiconductor memory device according to the first invention comprises: a memory cell array including a matrix of memory cells arranged along line and row directions, each memory cell being formed within a memory cell region; a plurality of first-layer bit lines extending along the row direction, each provided on a plurality of the memory cell regions; and a plurality of second-layer bit lines, each of which is connected with the first-layer bit line via a connecting hole; wherein the memory cell regions include first memory cell regions on which the connecting hole is provided, and second memory cell regions on which the connecting hole is not provided, and wherein at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of serving an electrical memory operation.
The semiconductor memory device according to the second invention comprises: a memory cell array including a matrix of memory cells arranged along line and row directions, each memory cell being formed within a memory cell region; a plurality of first-layer bit lines extending along the row direction, each provided on a plurality of the memory cell regions; and a plurality of second-layer bit lines, each of which is connected with the first-layer bit line via a connecting hole; wherein the memory cell regions include first memory cell regions on which the connecting hole is provided, and second memory cell regions on which the connecting hole is not provided, and wherein at least one of the memory cells formed within the memory cell regions adjacent to the first memory cell regions along the line direction is a dummy cell incapable of serving an electrical memory operation.
In the semiconductor memory device according to the third invention, each memory cell is connected with a pair of the first-layer bit lines, one of the pair of the first-layer bit lines is connected with one of the second-layer bit lines through the connecting hole within the memory cell region of the dummy cell, and another one of the pair of the first-layer bit lines is connected with one of the second-layer bit lines through the connecting hole within the memory cell region of the memory cell capable of serving the electrical memory operation.
In the semiconductor memory device according to the fourth invention, two or four of the memory cell regions of the dummy cells are arranged in series along the row direction.
Also, the semiconductor memory device according to the fifth invention further comprises: a plurality of dummy cell bit lines connected with the dummy cells for maintaining the dummy cells to a GND potential.
In the semiconductor memory device according to the sixth invention, the memory cell array further includes a GND line extending along the row direction, each of the dummy cell is connected with the GND line via the dummy cell bit lines.
In the semiconductor memory device according to the seventh invention, each of the dummy memory cell includes a pair of memory node portions and a pair of load transistors with drain-source regions, and each drain-source region is disconnected with any of the memory node portions.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the sprit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5280441 (1994-01-01), Wada et al.
patent: 5379248 (1995-01-01), Wada et al.
patent: 5563820 (1996-10-01), Wada et al.
patent: 5699308 (1997-12-01), Wada et al.
patent: 5892704 (1999-04-01), Lattimore et al.
patent: 6009010 (1999-12-01), Ohkubo
patent: 4322460 (1992-11-01), None
patent: 6259968 (1994-09-01), None

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