Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1991-11-12
1993-11-30
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Plural blocks or banks
365203, G11C 800, G11C 700
Patent
active
052672158
ABSTRACT:
In a semiconductor memory device, a transfer gate is disposed for each bit line, which classifies the bit lines, word lines, and memory cells at intersections therebetween into a plurality of groups. In a memory operation, portions of bit lines not employed in the operation are disconnected from sense amplifiers, which prevents charge and discharge operations from occurring therethrough. Consequently, the current which is caused by the charge and discharge operations through the bit lines and which occupies most portions of the current appearing in the memory device can be minimized, thereby reducing the total current flowing therethrough.
REFERENCES:
patent: 4050061 (1977-09-01), Kitagawa
patent: 4370575 (1983-01-01), McAlexander, III et al.
patent: 4520465 (1985-05-01), Sood
patent: 4528646 (1985-07-01), Ochii et al.
patent: 4777625 (1988-10-01), Sakui et al.
patent: 4926382 (1990-05-01), Sakui et al.
patent: 4969125 (1990-11-01), Ciraula et al.
patent: 4977538 (1990-12-01), Anami et al.
patent: 4982372 (1991-01-01), Matsuo
patent: 5051954 (1991-09-01), Toda et al.
patent: 5124948 (1992-05-01), Takizawa et al.
patent: 5172335 (1992-12-01), Sasaki et al.
Kessell Michael C.
LaRoche Eugene R.
NEC Corporation
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