Semiconductor memory device with testable spare columns and rows

Details Semiconductor memory device with testable spare columns and rows Semiconductor memory device with testable spare columns and rows

1999-03-17

2000-04-04

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 800

Patent

active

060469552

ABSTRACT:
A synchronous dynamic random access memory has spare columns which can be tested before shipping. In the memory, a mode set register outputs a multibank write signal in the test mode. A CBS latch circuit generates not only a signal for selecting the spare column decoders in banks and in the test mode but also signals for selecting the column decoders. Write driving circuits write the data onto the column lines selected by the column decoders and onto the spare column lines selected by the spare column decoders.

REFERENCES:
patent: 5379259 (1995-01-01), Fujita
patent: 5740119 (1998-04-01), Asakura et al.

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