Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-09-03
2004-11-16
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185090
Reexamination Certificate
active
06819596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a pulse generator circuit and an internal voltage generator circuit, the semiconductor device being capable of adjusting values of a pulse width of the pulse generated by these circuits and a value of an internal voltage. More particularly, the present invention relates to a nonvolatile semiconductor memory that internally generates a reference voltage, a writing voltage, a erasure voltage, and a readout voltage.
2. Description of the Related Art
An NAND type flash memory that is one type of nonvolatile semiconductor memory is announced by literature such as K. Imamiya et. al. “A 130-mm
2
256-Mb NAND Flash with Shallow Trench Isolation Technology”, IEEE J. Solid State Circuits, Vol. 34, pp. 1536-1543, November 1999” or the like.
In such a nonvolatile semiconductor memory, voltage trimming and defective cell redundancy replacement are carried out in a wafer test process.
FIG. 35
is a flowchart showing an outline of a conventional wafer testing process. The operating contents of each process are as follows.
In a DC test, DC checks such as contact check and standby current are made. In Vref (reference voltage) trimming, Wref of each chip on a wafer is monitored, and then, it is computed as to what a trimming value should be determined inn order to correct these to a target value.
Next, Vpgm (writing voltage) initial value trimming is carried out. In a NAND type flash memory, there is employed Incremental Step Pulse Programming Scheme that increments a writing voltage Vpgm from an initial value in a stepwise manner. This method is described in “K. D. Suh et. al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, “ISSCC Digest of Technical Papers, pp. 128-129, February 1995”, for example. In this writing method, it is required to optimize an initial value of Vpgm in order to ensure that a write time (or write loop count) is included within a predetermined time (count). For that purpose, it is required to find a block (good block) that can be written and erased from the inside of a memory cell array. This is because redundancy replacement of a defective cell is not carried out at this step.
If a good block is found, writing is carried in that block while an initial value of Vpgm is changed, and an optimal value is determined.
Subsequently, voltage trimming fuse cutting is carried out. At this step, a wafer is moved to a laser blow unit, and fuse cutting is carried out according to the above Vref trimming and a trimming value determined by Vpgm initial value trimming.
Subsequently, defective column/row detection is carried out. Here, for redundancy replacement, some data patterns are written into a memory cell array, and a defective column/row is detected.
Next, redundancy fuse cutting is carried out. Here, a wafer is moved to a laser flow unit again, and fuse cutting of redundancy replacement is carried out.
In this flowchart, voltage trimming fuse cutting is carried out before detecting a defective column/row because there is a possibility that, if defective column/row detection is carried out in a state in which an internally generated voltage such as Vpgm is shafted, a defect cannot be found.
A testing time at the above described wafer testing step is reflected in chip cost. Therefore, in order to reduce a chip cost, it is required to reduce a test time to the minimum while required wafer testing is carried out.
At the above described wafer test step, there are two factors that a test time is increased. One lies in the existence of a fuse cut step itself. In order to carry out fuse cutting by means of laser blowing, it is required to remove a wafer from a tester, and move the wafer to a laser blow unit. Here, a time overhead is produced. At the above described wafer test step, in particular, it is required to carry out fuse cutting separately twice, thus making the overhead more significant.
The second factor lies in a tester computation time, in order to reduce a test time, commands are assigned to about 100 chips at the same time at the wafer test step, and a tester is used such that an output can be measured at the same time. However, such a tester cannot carry out completely in parallel an operation for computing a trimming value from a monitored voltage or an operation for detecting a defective column row from a readout data pattern. A maximum of 10 chips can be processed in parallel. Therefore, even if data for 100 chips can be acquired at the same time, operational processing for such data must be carried out by being divided by 10 times, and here, a time overhead occurs.
A method for reducing a time for the fuse cutting step of the above two factors is described by the invention relating to application of Japanese Patent Application Publication No. 11-351396 made by the Applicant. The outline is given below.
In a nonvolatile semiconductor memory, a memory cell can store information in a nonvolatile manner. Thus, if a voltage trimming value or redundancy information is stored in a memory cell array, fuse and fuse cutting step can be eliminated. When a nonvolatile semiconductor memory is placed in a normal operation state, although it is required to store the previous trimming value or redundancy information in a predetermined register, the storage operation, i.e., an operation for acquiring information from the inside of a memory cell array, thereby storing the information in a register may be carried out at a time when a power is supplied to a nonvolatile semiconductor memory.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor device comprising:
a bit line;
a plurality of memory cells connected to the bit line; and
a sense amplifier connected to one end of the bit line; and
a defect detector circuit configured to read out data by the sense amplifier while setting a plurality of memory cells connected to the bit line all to a non-selected state, and the other end of the bit line being connected to a predetermined potential via a switch, and an open-circuit defect of the bit line being detected according to a readout data by the sense amplifier.
According to another aspect of the present invention, there is provided a semiconductor device comprising:
a memory cell array in which programmable and erasable nonvolatile memory cells are arranged in column and row directions of a matrix;
an address register that can store an address of a unit of memory cells which are programmed and erased simultaneously in the memory cell array; and
a control circuit that carries out an erase verify operation configured to output a “pass” or “fail” signal according to whether or not all the memory cells targeted for erasing are erased, a write verify operation configured to output the “pass” or “fail” signal according to whether or not all the memory cells targeted for writing are written, and an operation activated upon receipt of a first command, for, when either of results of the erase verify and write verify operations is “fail”, changing data of the address register, and when the results are “pass”, disabling change of data of the address register.
According to a further aspect of the present invention, there is provided a semiconductor device comprising a register activated by a command input, the register having plural types of test operations configured to output a “pass” or “fail” signal, wherein, if a result of an immediately preceding test that has been carried out of the test operations is “pass”, no data is changed, and if the result is “fail”, data is set in a predetermined signal state.
According to a further aspect of the present invention, there is provided a semiconductor device having erase verify and write verify functions comprising:
memory cells;
an address register that can store an address of a unit of memory cells which are programmed and erased simultaneously in the memory cell array;
a first register that stores a “pass” and “fail” result after an erase veri
Himeno Toshihiko
Ikehashi Tamio
Takeuchi Ken
Auduong Gene N.
Banner & Witcoff , Ltd.
Kabushikia Kaisha Toshiba
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