Semiconductor memory device with test circuit

Details Semiconductor memory device with test circuit Semiconductor memory device with test circuit

1990-02-14

1993-02-09

Baker, Stephen M.

Excavating

371 213, 371 211, G11C 2900

Patent

active

051857448

ABSTRACT:
A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding match lines (ML1 to ML4). A flag compress (30) performs a logic operation on the test results outputted to the plurality of match lines (ML1 to ML4) and outputs the operation results as test results for the plurality of memory array blocks (B1 to B4) to the outside.

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