Semiconductor memory device with synchronous dram whose speed gr

Details Semiconductor memory device with synchronous dram whose speed gr Semiconductor memory device with synchronous dram whose speed gr

1995-09-26

1996-08-27

Zarabian, A.

Static information storage and retrieval

Addressing

Sync/clocking

365236, G11C 800

Patent

active

055507840

ABSTRACT:
The semiconductor memory device disclosed includes a burst counter in a first stage of pipeline, a column switch latch portion in a second stage of the pipeline and an output data latch circuit in a third stage. In the operation mode with CAS latency of 2, as a control signal of the burst counter, a clock signal is outputted and, as a control signal of the column switch latch portion, a logical sum OR fixed to a high level by a mode signal is outputted. The device further includes a delay circuit and an output controller. The data output circuit is arranged such that it supplies, as a control signal of the output data latch circuit, a logical product AND of the inversion of the mode signal and the clock signal, and a logical sum OR of a signal delayed through the delay circuit and a logical product AND of the mode signal. In the synchronous DRAM thus configured, the speed grade in the operation mode with CAS latency of 2 is not restricted.

REFERENCES:
patent: 5430680 (1995-07-01), Parris
patent: 5454097 (1995-09-01), Babin
NEC Technical Reports, vol. 47, No. 3, 1994, pp. 76-77.

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