Semiconductor memory device with switching circuit for controlli

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371 276, G11C 2900

Patent

active

059369752

ABSTRACT:
A semiconductor memory device includes a burst counter for receiving an external address signal and generating an internal address signal for a predetermined burst length in synchronization with an external clock, and a switching circuit arranged such that, during the test mode, an address signal to be inputted to a column decoder which receives and decodes said internal address signal is switched, unlike under a normal mode, to be variable at each cycle, and a column select line to be outputted from said column decoder is configured so as to be variable at each cycle. The switching circuit may include first P-type transistors together with N-type transistors for selectively inputting predetermined lower order bits of said internal address signal to one of a decoder and a column decoder, second P-type transistors for selectively placing predetermined upper order bits of internal address signal to be in one of a conductive state and a non-conductive state with respect to said column decoder, and a latch circuit for holding values of said predetermined upper order bits. Because of the switching circuit, a parallel test for a plurality of cells can be carried out efficiently.

REFERENCES:
patent: 4393457 (1983-07-01), New
patent: 5550784 (1996-08-01), Takai
patent: 5566124 (1996-10-01), Fudeyasu et al.
patent: 5629903 (1997-05-01), Agata
patent: 5675549 (1997-10-01), Ong et al.

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