Semiconductor memory device with single clock signal line

Details Semiconductor memory device with single clock signal line Semiconductor memory device with single clock signal line

2002-04-02

2003-06-03

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189020

Reexamination Certificate

active

06574163

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a synchronous type semiconductor memory device of a double data rate.
2. Description of the Related Art
Conventional, a memory apparatus like 128-M DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access the memory) is known.
FIGS. 1A and 1B
are block diagrams showing the outline circuit structure of the memory apparatus. Referring to
FIGS. 1A and 1B
, the memory device is comprised of a clock signal generating section
120
, a memory cell array
1
102
-
1
, a memory cell array
2
102
-
2
, a data amplifier
1
106
-
1
, a data amplifier
2
106
-
2
and an output circuit
108
. The clock signal generating section
120
generates internal clock signals ICLK
1
and ICLK
2
from an external clock signal ECLK and a signal ECLKB as an inversion signal of the signal ECLK. A column decoder (not shown) to specify a Y address and a sense amplifier (not shown) to detect data read from a memory cell are provided in each of the memory cell array
1
102
-
1
and the memory cell array
2
102
-
2
. The output circuit
108
has a multiplexer (MUX)
110
and an output latch buffer
114
.
Data is read out from the memory cell array
1
102
-
1
, is amplified by the data amplifier
106
-
1
and is outputted on a data bus
10
L. Also, data is read from the memory cell array
2
102
-
2
, is amplified by the data amplifier
106
-
2
and is outputted on a data bus
20
L. If the data on the data bus
10
L is an odd number side, the data on the data bus
20
L is an even number side, and if the data on the data bus
10
L is the even number side, the data on the data bus
20
L is the odd number side.
The multiplexer (MUX)
110
of the output circuit
108
outputs the data on the data buses
10
L and
20
L to the output latch buffer
114
via a data bus Mout in order in response to the two internal clock signals ICLK
1
and ICLK
2
which are supplied from the clock signal generating section
120
. The output latch buffer
114
outputs the data from the multiplexer (MUX)
110
to an output terminal Dout in order in response to the external clock signals ECLK and ECLKB. In this way, the data of the odd number side and the data of the even number side are outputted during one period of the external clock signal.
FIGS. 2A
to
2
H are timing charts showing an operation of the conventional memory device shown in
FIGS. 1A and 1B
. As shown in
FIGS. 2A and 2B
, the external clock signals ECLK and ECLKB are supplied to the clock signal generating section
120
. As shown in
FIGS. 2C and 2D
, the clock signal generating section
120
generates the internal clock signals ICLK
1
and ICLK
2
from these external clock signals ECLK and ECLKB. That is, the internal clock signals ICLK
1
and ICLK
2
are generated to synchronize with the rising edge or falling edge of the external clock signals ECLK or ECLKB, respectively. In this way, the internal clock signals ICLK
1
and ICLK
2
have the frequency the same as the external clock signal. The internal clock signals ICLK
1
and ICLK
2
have approximately the same phase as the external clock signals ECLK and ECLKB.
The data DATA
1
of the odd number side and data DATA
2
of the even number side read out from the memory cell array
1
102
-
1
and the memory cell array
2
102
-
2
are amplified by the data amplifiers
106
-
1
and
106
-
2
and are outputted on the data buses
10
L and
20
L during one period of the internal clock signal, respectively, as shown in
FIGS. 2E and 2F
.
The above internal clock signals ICLK
1
and ICLK
2
are supplied to the multiplexer (MUX)
110
. As shown in
FIG. 2G
, the multiplexer (MUX)
110
selects the data DATA
1
on the data bus
10
L in response to the rising edge of internal clock ICLK
1
and outputs it to the output bus Mout. Next, the multiplexer
110
selects the data DATA
2
on the data bus
20
L in response to the rising edge of the internal clock ICLK
2
(the falling edge of the internal clock ICLK
1
) and outputs it to the output bus Mout. As shown in
FIG. 2H
, the output latch buffer
114
outputs the data DATA
1
and DATA
2
from the output terminal Dout in response to the external clock signals ECLK and ECLKB, respectively. In this way, the two data DATA
1
and DATA
2
can be read out during one period of the external clock signal.
In such a DDR-SDRAM, a layout is often used in which a plurality of memory cell arrays are arranged on both sides of a chip, and a single clock signal generating section
120
is arranged on the center of the chip. The output circuit
108
containing the multiplexer
110
is provided for each memory cell array. The two internal clock signals ICLK
1
and ICLK
2
generated by the clock signal generating section
120
are supplied to each output circuit
108
as a pair, as shown in FIG.
3
.
In 256-MB DDR-SDRAM, a clock signal of 166 MHz is used as the external clock signal, whose one cycle is about 6 ns. In this case, one read cycle is about 3 ns. When a high frequency clock signal is used in this way, there is a case where data cannot be read out right due to the difference between the propagation delay times of the internal clock signal, when the wiring lines for the internal clock signals are different in the length from the clock signal generating section
120
to each output circuit
108
. For this reason, the wiring line of the internal clock signal is generally designed for the wiring lengths from the clock signal generating section
120
to the respective output circuits
108
to be equal, for elimination of the difference in the propagation delay time. For this purpose, as shown in
FIG. 3
, the wiring lines for the two internal clock signals ICLK
1
and ICLK
2
needs be arranged to be equal in length for the output circuits. However, in the conventional DDR-SDRAM, the mask design becomes complicated and also a chip area is wasted. Especially, when a multiple bit output circuit structure is adopted like the 16-bit output, the arrangement of the clock signal wiring lines becomes very difficult.
Also, as mentioned above, when the internal clock signal is generated using the rising edge or falling edge of the external clock signal, there is no guarantee that the duty ratio of the internal clock signal is 50%. When the duty ratio is not 50%, the durations of the internal clock signals ICLK
1
and ICLK
2
in the high level are different, and there is a case that the operation margin cannot be secured.
In addition, in a high speed operation DDR-SDRAM, because the period of the read cycle is short, the margin for the setup reduces. Therefore, it is desirable that the internal clock signal used for the reading operation is supplied before the reading cycle. Contrary, when the internal clock signal is too early supplied, the internal clock signal is supplied before the previous cycle ends so that there is possibly erroneous operation.
In conjunction with the above description, a clock system of a semiconductor memory device which uses a frequency multiplier is disclosed in U.S. Pat. No. 6,157,238. In this reference, an external clock signal source generates external clock signals. A controller has a master frequency amplifier and a master DLL circuit. Each of a plurality of DRAMs has the frequency multiplier and the DLL circuit. The frequency multiplier generates an internal clock signal, which has twice of the frequency of the external clock signal, from the external clock signal. The frequency multiplier has a delay circuit, a logical device and a buffer. The delay circuit generates a phase delayed clock signal based on the external clock signal. The logical device generates the internal clock signal based on the external clock signal and the phase delayed clock signal. The buffer buffers the internal clock signal and supplies it.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2000-298983A). In this reference, the semiconductor memory device has first and second memory sections and an output sect

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