Semiconductor memory device with shorter signal lines

Details Semiconductor memory device with shorter signal lines Semiconductor memory device with shorter signal lines

2001-03-19

2004-07-06

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S218000, C365S185110, C365S185290, C365S189040

Reexamination Certificate

active

06760271

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a page-mode memory device that allows a plurality of pages to be accessed at high speed.
2. Description of the Related Art
Page-mode memory devices allow high-speed data write/read operation to be performed with respect to a memory cell array. In page-mode memory devices, data is read from a plurality of pages at once to be stored in the sense amplifiers, and an address is provided from an exterior of the device to specify a page, thereby reading the data of the specified page at high speed. As long as the specified page is one of the plurality of pages that have been read at once, all that is required is to read data from the sense amplifiers, and there is no need to read data by accessing the memory cell array each time a page is specified. This shortens a time period from the address input to the data output, thereby achieving high-speed data read operation.
FIG. 1
is an illustrative drawing showing a configuration of a related-art page-mode memory.
A memory cell array
10
is divided into four pages Page
0
through Page
3
, and each page is further divided into portions corresponding to respective input/output terminals. For example, an input/output terminal I/O
0
is coupled to a corresponding portion of each memory cell array through a corresponding input/output buffer
11
and a corresponding sense amplifier
12
. The same applies in the case of other input/output terminals. In this manner, each input/output terminal is coupled to all of these four pages Page
0
through Page
3
.
At the time of data read operation, data of all the pages Page
0
through Page
3
are read and stored in the sense amplifiers
12
. Thereafter, switches
13
for a selected page is switched on to supply the data of the selected page to an exterior of the memory device.
At the time of data write operation, all input/output terminals that correspond to a selected address are treated as one unit, and data is provided to perform write operation.
In the configuration of
FIG. 1
, the input/output buffers
11
are connected to the corresponding sense amplifiers
12
via signal lines
14
. Since each input/output terminal needs to be coupled to all the pages, the signal lines
14
tend to extend a long distance in commensurate with the spatial extension of the memory cell array corresponding to the four pages Page
0
through Page
3
.
Accordingly, wire resistance and capacitance of the signal lines
14
tend to be great, resulting in long signal delays. This causes a decrease in data write/read operation speed, hindering an effort toward the higher operation speed of memory chips.
Accordingly, there is a need for a semiconductor memory device that can achieve high-speed operation by reducing wire resistance and capacitance of signal lines associated with the input/output section of the memory device.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device including a plurality of input/output terminals, a memory cell array which are divided into blocks respectively corresponding to the input/output terminals such that only one of the blocks corresponds to a given one of the input/output terminals, sense amplifiers, which are connected to the blocks at a side thereof, and amplify data of the memory cell array, switches which are respectively connected to the sense amplifiers, and signal lines, which connect the sense amplifiers to a corresponding one of the input/output terminals via the switches.
According to the present invention as described above, a given input/output terminal is coupled to only one block of the memory cell array where this one block corresponds to this input/output terminal, so that the signal lines connecting the input/output terminal to the sense amplifiers suffice if they have a line length substantially comparable to the spatial extension of the block. In other words, the signal lines connecting the input/output terminal to the sense amplifiers only need to be coupled to the sense amplifiers corresponding to the plurality of pages, so that a length of the signal lines are sufficient if it is comparable to the spatial extension of these sense amplifiers arranged adjacent to one another. Accordingly, the semiconductor memory device of the present invention can achieve high-speed operation by reducing wire resistance and capacitance of the signal lines associated with the input/output section of the device.
According to another aspect of the present invention, a semiconductor memory device includes an electrically rewritable nonvolatile memory cell array which include a plurality of I/O portions, which are grouped into a plurality of I/O sets, word lines provided separately for respective ones of the I/O sets, and word-line drivers provided separately for the respective ones of the I/O sets, wherein the word lines are activated in all the I/O sets during a read operation, and are activated in at least one but not all of the I/O sets during a write operation.
The present invention described above reduces a stress that is applied to the gates of memory cells during write operation when the word lines are activated to a high potential. This helps to improve reliability of the data.


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