Semiconductor memory device with serial access memory

Details Semiconductor memory device with serial access memory Semiconductor memory device with serial access memory

1988-12-01

1990-05-29

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiplexing

365239, 36523009, G11C 700

Patent

active

049301080

ABSTRACT:
A semiconductor memory device includes: a first memory cell array having a plurality of memory cells arrayed in a row direction and a column direction; a second memory cell array having at least serial access memory cells corresponding to a single row of the first memory cell array; a first data bus; a second data bus; a third data bus; and a bus switching control circuit for controlling a connection of each of the serial access memory cells to one of the first, second and third data buses and selecting one of the buses to connect the selected data bus to the external of the device. The bus switching control circuit outputs each of bit data in the serial access memory cells serially and alternately to the first and second data buses and, where a plurality of transfer data blocks are serially read out from the second memory cell array, outputs a bit data in the serial access memory cell corresponding to the head or last address in each of the transfer data blocks to the third data bus. As a result, it is possible to prevent interruption from being generated between the transfer data blocks in the serial data transfer operation and thus to increase the data transfer speed.

REFERENCES:
patent: 4633441 (1986-12-01), Ishimoto
patent: 4733376 (1988-03-01), Ogawa
patent: 4757477 (1988-07-01), Nagayama et al.

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