Semiconductor memory device with sense amplifier

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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C365S063000

Reexamination Certificate

active

06879539

ABSTRACT:
A semiconductor memory device that can be reduced in chip area while preventing degradation in characteristic is obtained. In DRAM, a plurality of memory cell array regions are arranged in matrix, spaced apart from each other in a row direction and in a column direction, on a semiconductor substrate. A sense amplifier region is arranged in a gap between the memory cell array regions in the column direction. An element forming a sense amplifier is arranged in the sense amplifier region. A subdecoder region is arranged in a gap between the memory cell array regions in the row direction. A cross region is arranged at an intersection of the sense amplifier regions in line and the subdecoder regions in line. A sense amplifier driver element is arranged in the subdecoder region and used in a sense amplifier operation.

REFERENCES:
patent: 6226208 (2001-05-01), Nakai et al.
patent: 6288925 (2001-09-01), Kitsukawa et al.
patent: 9-64308 (1997-03-01), None
patent: 2000-22108 (2000-01-01), None

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