Semiconductor memory device with restrained scale of...

Details Semiconductor memory device with restrained scale of... Semiconductor memory device with restrained scale of...

2001-02-16

2002-04-16

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06373775

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device that performs redundancy relief of a defective memory cell by the shift redundancy method.
2. Description of the Background Art
In order to realize a wide memory band width required by some applications such as image processing, a memory device having numerous data I/O lines is developed beginning with a mixed DRAM/logic mounted memory in which a logic circuit and a memory device are mounted on one and the same chip. In such a memory cell array configuration having numerous data I/O lines, the shift redundancy method is used as a redundancy relief method for performing substitution of a defective memory cell.
FIGS. 19A and 19B
are schematic diagrams describing the substitution of a defective memory cell by the shift redundancy method.
FIG. 19A
shows a connection state of the data I/O lines in the case where the normal memory cell array is free from defects.
Referring to
FIG. 19A
, a group of normal I/O lines NIOs are provided in correspondence with a normal memory cell array, and spare I/O lines SIO
1
and SIO
2
are provided in correspondence with a spare memory cell array for redundancy relief. The NIOs, SIO
1
, and SIO
2
that transmit data input into and output from these inner memory cell array are connected to a group of external I/O lines EIOs that are capable of communicating data to and from the outside via a selector circuit
510
.
If the normal memory cell array is free from defects, there is no need to perform redundancy relief with the use of the spare memory cell array, so that the normal I/O lines NIOs and the external I/O lines EIOs are connected by the selector circuit
510
. On the other hand, the spare I/O lines SIO
1
and SIO
2
are not connected with the external I/O lines EIOs.
FIG. 19B
shows a connection state of the data I/O lines in the case where the normal memory cell array has a defect.
Referring to
FIG. 19B
, it is assumed that, in the normal memory cell array, regions corresponding to the normal I/O lines NB
1
and NB
2
marked with the symbol “×” have a defective memory cell. In this case, the defective memory cell is relieved by performing the redundancy relief in a unit of one I/O line. In other words, by switching the connection mode between the group of I/O lines on the inner side and the group of external I/O lines with the use of the selector circuit
510
, the data input/output is performed on the spare memory cell array, by accessing the spare I/O lines instead of accessing the normal I/O lines corresponding to the regions having a defective memory cell.
Thus, in the shift redundancy method, even in the case where the normal memory cell array part has a defective memory cell, the spare memory cell array is also accessed routinely, and at the stage of giving and receiving data to and from the external I/O lines, the switching mode among the data I/O lines in the selector circuit
510
is switched so as to substitute for the defective memory cells on the basis of information that is programmed in advance.
Therefore, the redundancy relief can be carried out at a high speed without causing any loss of access time necessary for the determination of redundancy by address comparison.
However, the shift redundancy method requires a shift switch for switching connection of each data I/O line and a decoding circuit for designating the connection mode in each switch by decoding the information programmed in advance.
For this reason, in a configuration where numerous data I/O lines are provided, the increase in the circuit area brought about by the decoding circuit cannot be ignored.
In order to solve these problems, a technique for simplifying the configuration of the decoding circuit of the shift switch in the shift redundancy method is disclosed, for example, in “Dynamically Shift-Switched Dataline Redundancy Suitable for DRAM Macro with Wide Data Bus”, Namekawa et al., 1999 Symposium on VLSI Circuits Digest of Technical Papers, pp. 149-152 (hereafter referred to as prior art).
FIG. 20
is a diagram related to the control of the shift switch in the shift redundancy method according to the prior art.
FIG. 20
shows a shift switch SFW for one I/O line and comparators CMP
1
and CMP
2
for controlling the connection mode of the shift switch SFW. Each of DQ
0
to DQ
2
is one of 128 DQs.
Referring to
FIG. 20
, the DQ address for indicating the I/O line number to which each shift switch SFW corresponds is set in advance by a wired logic.
In the shift redundancy method in accordance with the prior art, the shift switch corresponding to the I/O line having a defective memory cell is designated to be a shift position, and by utilizing the fact that the connection direction of each shift switch is the same in each of the right/left regions separated at the shift switch corresponding to the shift position, the connection direction in each shift switch is set by comparing the DQ address of its own and the DQ address designated to be the shift position in each shift switch instead of decoding the connection direction for each shift switch.
The comparators CMP
1
and CMP
2
compare the positional relationship between the DQ address and the predecoding signals Z
1
and Z
2
for designating the DQ address corresponding to the shift position, and determines which of the right/left regions of the shift position the corresponding shift switch SFW belongs, thereby to set the connection direction of the shift switch SFW.
This eliminates the need for instructing the connection direction for each shift switch, so that the number of bits in the predecoding signal can be reduced, and the configuration of the comparators CMP
1
and CMP
2
can be simplified.
Thus, the prior art aims at simplification of the decoding circuit, i.e. the comparators CMP
1
and CMP
2
, by utilizing the fact that the connection direction of the shift switch changes uniformly at the shift position. However, in accordance with the recent development of image processing technique and others, a wider data I/O width is demanded in increasing number of cases, so that a further simplification of the decoding circuit of the shift switch in the shift redundancy method is an important goal to be achieved.
SUMMARY OF THE INVENTION
The present invention provides a configuration of a semiconductor memory device that can reduce the area of the decoding circuit for setting the connection direction of the shift switch used in the shift redundancy method.
In summary, the present invention is directed to a semiconductor memory device including a memory cell array, a plurality of internal data lines, a plurality of external data lines, a plurality of shift switches, and a shift control circuit.
The memory cell array includes a normal memory array part and a spare array part disposed adjacent to the normal memory array part for substitution of a defective part in the normal memory array. The plurality of internal data lines transmit data input and output to and from the memory cell array part. The plurality of internal data lines include a plurality of normal data lines from the first one to the M-th one (M: natural number) disposed in correspondence with the normal memory array part, and a spare data line disposed in correspondence with the spare array part. The plurality of external data lines are capable of giving and receiving data to and from the outside, and consist of M lines from the first one to the M-th one. The plurality of shift switches are disposed in correspondence with the plurality of external data lines, respectively. The shift switches are each disposed between adjacent two lines in the plurality of internal data lines, and connect the corresponding external data line to either one of the adjacent two internal data lines in accordance with the instructed connection direction. The shift control circuit sets the connection direction of each shift switch on the basis of information on a shift position stored in advance in

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