Semiconductor memory device with redundant memory cells

Details Semiconductor memory device with redundant memory cells Semiconductor memory device with redundant memory cells

1988-09-09

1989-12-05

Popek, Joseph A.

Excavating

365200, G11C 700

Patent

active

048857211

ABSTRACT:
There is disclosed a semiconductor memory device having a redundant decoder units each storing a row address assigned to a defective memory cell replaced with a redundant memory cell, and a redundant state detection unit provided with an address detecting section operative to produce a first detecting signal when a row address represented by a row address signal is identical with one of the row addresses respectively stored in the redundant decoder units, and the address detecting section comprises a single bypassing transistor coupled between a first node applied with a first voltage level and a second node where the first detecting signal appears, a single bootstrapping circuit operative to supply a gate electrode of the bypassing transistor with a second voltage level higher than the first voltage level by a value slightly lower than a threshold voltage of the bypassing transistor, and a plurality of activating transistors coupled in parallel between a source of a third voltage level and the bootstrapping circuit and having respective gate electrodes coupled to the redundant decoder units, respectively, so that the bypassing transistor and the bootstrapping circuit are shared by all of the redundant decoder units, thereby reducing the component transistors.

REFERENCES:
patent: 4635190 (1987-01-01), Meyer et al.

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