Semiconductor memory device with reduced power consumption and r

Details Semiconductor memory device with reduced power consumption and r Semiconductor memory device with reduced power consumption and r

1994-07-06

1995-07-18

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

36518907, G11C 700

Patent

active

054348242

ABSTRACT:
A semiconductor memory device includes a memory cell array formed of a plurality of memory cells, a peripheral circuit supplied with address signals for selecting a memory cell in the memory cell array, the peripheral circuit further conducting a reading of the content of information stored in the selected memory cell and producing an output indicative thereof, and an address transition detection circuit for detecting a transition in any of the address signals and further for detecting a transition of the output of the peripheral circuit, wherein the address transition detection circuit activates the peripheral circuit when a transition has occurred in any of the address signals and the output of the peripheral circuit.

REFERENCES:
patent: 4959816 (1990-09-01), Iwahashi et al.
patent: 4972374 (1990-11-01), Wang et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device with reduced power consumption and r does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with reduced power consumption and r, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with reduced power consumption and r will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2421418