Semiconductor memory device with reduced number of...

Details Semiconductor memory device with reduced number of... Semiconductor memory device with reduced number of...

2007-07-17

2007-07-17

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290, C365S185330

Reexamination Certificate

active

11058192

ABSTRACT:
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potential on the word lines and bit lines according to the input data. The control circuit further controls the operations of writing data into, reading data from, and erasing data from the memory cells. A data storage circuit is connected to the bit lines and stores data under the control of the control circuit. The data storage circuit and the memory cell array are formed in the same well region.

REFERENCES:
patent: 6614684 (2003-09-01), Shukuri et al.
patent: 7016229 (2006-03-01), Kim
patent: 7023741 (2006-04-01), Nakamura et al.
patent: 8-46159 (1996-02-01), None

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