Static information storage and retrieval – Powering
Reexamination Certificate
2002-03-22
2003-11-18
Le, Thong (Department: 2818)
Static information storage and retrieval
Powering
C365S189110, C365S227000
Reexamination Certificate
active
06650590
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-095967, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic RAM (hereinafter referred to as a “DRAM”), and more particularly to a circuit for driving word lines.
2. Description of the Related Art
Recently, semiconductor memory devices have been microfabricated. In particular, DRAMs have an ultra-minute structure and operate on reduced power supply voltages. However, the threshold voltage of cell transistors of a DRAM cannot be reduced, as a leak current (Ioff), which flows when each cell transistor is not selected, is also reduced. This makes it difficult to scale the thickness of the gate oxide film of each cell transistor. In light of this, the thinning of the gate oxide film is realized, using, for example, a material with a high breakdown voltage. However, since the electric field (Eox) applied to the gate oxide film is not less than 6 MV/cm at present, the conventional method is approaching its limits.
To solve the problem, a so-called negative-word-line-reset (NWR) method is now being proposed. In this method, the word-line reset potential is set lower than the low level of bit lines (i.e. the potential used to write “0” data). Further, the gate-source potential Vgs is less than 0. Accordingly, the threshold voltage can be reduced, with the leak current Ioff kept low.
In the NWR method, when the bit-line potential varies between Vaa and Vss (Vaa>Vss(ground potential)), the word-line potential varies between a boosted voltage Vpp and a negative voltage Vnn (the reset potential of the word lines) (Vpp>Vnn, Vnn>Vss, Vpp>Vaa). This means that the word-line driving circuit needs a level shift circuit for generating, from a power supply voltage, the boosted voltage Vpp higher than the power supply voltage, and another level shift circuit for generating the negative voltage Vnn from the power supply voltage.
FIG. 11
schematically shows the core section of a standard DRAM configured for NWR. A plurality of memory cell arrays MCA have their respective segment word lines SWL and bit lines BL. A memory cell MC is provided at each intersection of the segment word lines SWL and bit lines BL. In other words, each memory cell array MCA includes a plurality of memory cells MC arranged in a matrix.
Segment-row-decoder groups SRD for selecting the segment word lines SWL are arranged at the opposite ends of the segment row lines SWL of each memory cell array MCA. Each segment-row-decoder group includes a plurality of segment row decoders (not shown) corresponding to the number of segment word lines. Further, a plurality of sense amplifiers S/A are arranged at the opposite ends of the bit lines of each memory cell array MCA. The potential of the bit lines BL is amplified by the sense amplifiers S/A.
A local word-drive-line driving circuit LWD and various driving circuits (not shown), etc. are provided in each intersection area (hereinafter referred to as an “SSC”) between the sense amplifiers S/A and the segment-row-decoder groups SRD. A plurality of local word drive lines LWDRV are connected to the local word-drive-line driving circuit LWD. The local word drive lines LWDRV are driven by the local word-drive-line driving circuit LWD, whereby they are connected to the respective row decoders of a corresponding segment-row-decoder group SRD.
A plurality of main word lines MWL are provided above those of the memory cell arrays MCA, which are arranged along the segment word lines SWL. The main word lines MWL are connected to main-row-decoder groups MRD arranged to correspond to the segment-row-decoder groups SRD. Each main-row-decoder group MRD includes a plurality of main row decoders. Each main row decoder selects a corresponding one of the main word lines MWL. In other words, the main word lines MWL are driven by the respective main row decoders of each main row decoder group WRD, whereby they are connected to the respective segment row decoders of each segment row decoder group SRD. The segment word lines SWL are driven by the respective segment row decoders, whereby they are connected to the respective memory cells of each memory cell array MCA. The area selected by each main decoder group MRD forms one block.
A block-select-line driving circuit BSD, for example, is provided in an area SMC located adjacent to each intersection area SSC between corresponding main row decoder groups MRD. The block-select-line driving circuit BSD is connected to a block select line BS. Each block select line BS is provided above corresponding intersection areas SSC and sense amplifiers S/A arranged in the direction of the segment word lines SWL. The block select lines BS are driven by the respective block-select-line driving circuits BSD, whereby they are connected to the respective local word-drive-line driving circuits LWD.
A column select line CSL is provided corresponding to those of the sense amplifiers S/A, which are arranged in the direction of each bit line BL. One end of each column select line CSL is connected to a column-select-line driving circuit CSLD. The column-select-line driving circuit CSLD is provided in each of areas AMP. A data-line sense amplifier (not shown), for example, is provided in each area AMP.
A global word-drive-line driving circuit GWD is provided in an area ASC, which is located adjacent to each intersection area SSC between corresponding areas AMP. A global word drive line GWDRV is connected to each global word-drive-line driving circuit GWD. The global word drive line GWDRV is provided corresponding to those of the intersection areas SSC and segment row decoders SRD, which are arranged in the direction of each bit line BL. The global word drive line GWDRV is connected to each global word-drive-line driving circuit GWD in a corresponding intersection area SSC. Further, various control circuits and/or driving circuits are provided in each area ASC.
As described above, in the NWR method, the potential of the segment word lines SWL is set at Vpp or Vnn. However, if the potential of an address signal or a control signal supplied from a peripheral circuit to the core section is set at Vpp or Vnn, the consumption of power, for example, may increase. Therefore, it is not preferable to set such a potential range. In light of this, these signals are generally set at an internal power supply voltage Vii or Vss. In the NWR method, the core section needs a level shift circuit for converting the internal power supply voltage Vii or Vss into the potential Vpp or Vnn.
In the circuit shown in
FIG. 11
, the level shift circuit only converts the internal power supply voltage Vii or Vss into the voltage Vpp or Vss. This being so, the level shift circuit is provided only in the local word-drive-line driving circuit LWD that is provided in each intersection area SSC.
FIG. 12
schematically shows a word line driving system example in a DRAM. The global word-drive-line driving circuit GWD drives the global word drive line GWDRV in accordance with an address signal Add (of the internal power supply voltage Vii or ground voltage Vss). The high and low levels of the global word drive line GWDRV are the internal power supply voltage Vii and the ground voltage Vss, respectively.
Each local word-drive-line driving circuit LWD includes first and second level shift circuits LS
1
and LS
2
and a driving circuit DR. The first level shift circuit LS
1
boosts the internal power supply voltage Vii into Vpp, while the second level shift circuit LS
2
converts the ground voltage Vss into the negative voltage Vnn. The driving circuit DR drives the local word drive line WDRV in accordance with output signals from the first and second level shift circuits LS
1
and LS
2
. The high and low levels of the local word drive line LWDRV are the boosted voltage Vpp and the negative v
Ikeda Toshimi
Inaba Tsuneo
Kohno Fumihiro
Tsuchida Kenji
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Thong
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