Semiconductor memory device with reduced current consumption

Details Semiconductor memory device with reduced current consumption Semiconductor memory device with reduced current consumption

2001-06-20

2003-03-04

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S207000, C365S189050, C365S189011

Reexamination Certificate

active

06529440

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device that can reduce consumption of electric currents.
2. Description of the Related Art
There are semiconductor memory devices for which the number of input/output data bits can be changed. This is achieved by changing the number of column selection lines or by switching the outputs of data bus amplifiers.
In such related-art methods, consumption of electric currents in the integrated circuit as a whole almost does not change even when the number of input/output data bits is changed. This is because the current consumption during an activation period is attributable to sense amplifiers, i.e., attributable to electric currents related to amplification of bit lines. Unless the number of activated sense amplifiers is reduced, a substantial reduction in the current consumption cannot be achieved in semiconductor memory devices.
If a circuit design or architecture is substantially changed for the purpose of reducing current consumption, however, such a change incurs undesirable costs. Accordingly, it is desired to achieve a semiconductor memory device having a low current consumption by employing substantially the same circuit structure and architecture as in the related art.
Accordingly, there is a need for a semiconductor memory device that can reduce current consumption in accordance with the number of input/output data bits by changing the number of activated amplifiers.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
It is another and more specific object of the present invention to provide a semiconductor memory device that can reduce current consumption in accordance with the number of input/output data bits by changing the number of activated amplifiers.
In order to achieve the above objects according to the present invention, a semiconductor memory device includes a DQ-quantity-selection signal generation circuit which generates a DQ-quantity-selection signal indicative of a number of input/output data bits, bit lines which transfer read data and write data for memory cells, and a plurality of sense amplifiers which are connected to the bit lines, and are activated as many as indicated by the DQ-quantity-selection signal.
In the semiconductor memory device as described above, the number of sense amplifiers that are activated is controlled in response to the DQ-quantity-selection signal indicative of the number of input/output data bits, thereby achieving a reduction in the current consumption of the semiconductor memory device.
According to another aspect of the present invention, the semiconductor memory device as described above further includes input/output terminals through which data is output to and input from an exterior of the semiconductor memory device, data bus amplifiers which are situated between the sense amplifiers and the input/output terminals, and amplify the read data and the write data, and a data bus amplifier selection circuit which selectively activates the data bus amplifiers in accordance with the DQ-quantity-selection signal.
In the semiconductor memory device as described above, the number of data bus amplifiers that are activated is controlled in accordance with the number of input/output data bits, thereby achieving a further reduction of current consumption in the semiconductor memory device.
According to another aspect of the present invention, the semiconductor memory device as described above further includes a circuit which activates circuitry contained in a sense amplifier row that is not activated.
In the semiconductor memory device as described above, even when a given sense amplifier row is not activated, circuitry that needs to be driven in this sense amplifier row can be activated. Such circuitry may include a circuit that generates a sub-word-decoder activation signal.
According to another aspect of the present invention, the semiconductor memory device as described above is such that the sense amplifiers are selectively activated by a column address.
In the semiconductor memory device as described above, activation of the sense amplifiers is controlled based on the column address selection, thereby achieving a substantial reduction in current consumption.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 5267198 (1993-11-01), Hatano et al.
patent: 5973983 (1999-10-01), Hidaka
patent: 6061297 (2000-05-01), Suzuki

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