Semiconductor memory device with readily changeable memory...

Details Semiconductor memory device with readily changeable memory... Semiconductor memory device with readily changeable memory...

2001-01-05

2001-12-25

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S230060, C365S230030

Reexamination Certificate

active

06333869

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to semiconductor memory devices with a memory block mounted thereon together with a logic circuit and thus used.
2. Description of the Background Art
There is a system LSI developed with a large-capacity dynamic random access memory (DRAM) and a large-scale logic circuit mounted thereon in a mixed manner. Such a system LSI has been materialized attributed to the recent advance of semiconductor microprocessing technology. It can incorporate a DRAM therein and have a memory bus width in a chip thereof that is extended without any limitation imposed thereon by an external terminal. For example, a bus width extended from 16 bits, as conventional, to multiple bits of 128-256 bits allows data to be rapidly transferred and digital devices to provide high performance and operate with reduced power consumption.
Such a system LSI as described above is often produced as an application-specific IC (ASIC). For the ASIC, a DRAM incorporated therein is required to have a core having a different memory capacity depending on the application.
FIG. 12
illustrates an arrangement of a circuit block having arranged therein a conventional DRAM core's memory cell array and sense amplifier.
As shown in
FIG. 12
, on opposite sides of a memory cell array MA#2 there are provided sense amplifier bands SAB#2 and SAB#3. On a side of sense amplifier band SAB#2, memory cell array MA#2 and sense amplifier band SAB#3 there are provided a column select control circuit
502
, a row select control circuit
504
, and a column select control circuit
506
, respectively. Sense amplifier band SAB#2, memory cell array MA#2 and sense amplifier band SAB#3 are adjacent to square regions, respectively, which will be referred to as a center cross circuit band CCCB#2, a center circuit band CCB#2 and a center cross circuit band CCCB#3,respectively. As such, column select control circuit
502
, row select control circuit
504
and column select control circuit
506
exist internal to center cross circuit band CCCB#2, center circuit band CCB#2 and center cross circuit band CCCB#3, respectively.
FIG. 13
is a block diagram for illustrating a signal input to the
FIG. 12
center cross circuit band CCCB#2.
With reference to
FIG. 13
, center circuit band CCB#1 includes a row predecode circuit
514
, an address latch circuit
512
, a row decoder
516
and a sense amplifier control circuit
518
.
Center circuit band CCB#2 includes a row predecode circuit
524
, an address latch circuit
522
, a row decoder
526
and a sense amplifier control circuit
528
. Row predecode circuit
524
, address latch circuit
522
, row decoder
526
and sense amplifier control circuit
528
correspond to the
FIG. 12
row select control circuit
504
.
Center cross circuit band CCCB#2 is provided with a row decode circuit
520
. Row decode circuit
520
corresponds to the
FIG. 12
column select control circuit
502
.
Row decoders
516
and
526
output to their respective adjacent memory cell arrays a signal MWLD<m:0> driving a main word line to select a memory cell row. In response to signal MWLD<m:0>, a memory cell array has a word line activated.
In response to a memory cell row having been selected, sense amplifier control circuit
528
connects a sense amplifier to a bit line and activates the sense amplifier. As such, conventionally, together with row predecode circuit
524
and row decoder
526
which are common in providing a row address processing, sense amplifier control circuit
528
is arranged as the
FIG. 12
row select control circuit
504
in center circuit band CCB#2 corresponding to a region adjacent to a memory cell array.
As such, sense amplifier control circuit
528
outputs a bit line equalization signal and a bit line isolation signal to both of sense amplifier band SAB#2 arranged between memory cell arrays MA#2 and MA#1 and a sense amplifier band SAB#3 (not shown). Furthermore, sense amplifier control circuit
528
outputs a sense amplifier activation signal SE, /SE to sense amplifier band SAB#2.
FIG. 14
is a circuit diagram showing a configuration of the
FIG. 13
address latch circuit
522
.
As shown in
FIG. 14
, address latch circuit
522
includes a latch circuit
532
latching a signal XBLK<n> in synchronization with a signal XLAT<bankn>, a latch circuit
534
latching a signal XBLK<n−1> in synchronization with signal XLAT<bankn>, and a latch circuit
536
latching a row address signal RA<k:0> in synchronization with signal XLAT<bankn>.
Latch circuit
532
outputs a signal XBLATL indicating that when memory cell array #n is selected, sense amplifier bands SAB#n and SAB#n+1 are connected to memory cell array #n to use a sense amplifier.
Latch circuit
534
outputs a signal XBLATR for activating a sense amplifier of sense amplifier band SAB#n when memory cell array #n−1 is selected.
Furthermore, latch circuit
536
holds and outputs a row address signal RALAT<k:0> input in response to a memory block having been selected. Row address signal RALAT<k:0> is input to and predecoded in the
FIG. 13
row predecode circuit
524
. The predecoded signal is fed to row decoder
136
to activate any one of signal MWLD<m:0> for driving a word line. Note that signal XBLK<n> corresponds to signal XBLK<2>.
Address latch circuit
512
is similar in configuration to the
FIG. 14
address latch circuit
522
and a description thereof will thus not be repeated, although for address latch circuit
512
, signal XBLK<n> corresponds to signal XBLK<1>.
FIG. 15
is a circuit diagram showing a configuration of the
FIG. 13
row decode circuit
520
.
As shown in
FIG. 15
, row decode circuit
138
includes an AND circuit
542
receiving a bank select signal YBANK<n> and a signal XBLATL output from address latch circuit
522
, an AND circuit
544
receiving a bank select signal YBANK<n> and a signal XBLATR output from address latch circuit
522
, an NOR circuit
546
receiving a signal output from AND circuit
542
and that output from AND circuit
544
, an inverter
548
receiving and inverting a signal output from NOR circuit
546
, an NAND circuit
556
receiving a column select signal CSLR<i:0> for read operation and a signal output from inverter
548
, an inverter
558
receiving and inverting a signal output from NAND circuit
556
, and an inverter
560
receiving and inverting a signal output from inverter
558
and outputting a signal CSLRD<i:0> driving a column select line.
Row decode circuit
520
also includes an NAND circuit
550
receiving a column select signal CSLW<i:0> for write operation and a signal output form inverter
548
, an inverter
552
receiving and inverting a signal output form NAND circuit
550
, and an inverter
554
receiving and inverting a signal output form inverter
552
and outputting a signal CSLWD<i:0> driving a column select line.
FIG. 16
is a circuit diagram showing a configuration of the
FIG. 13
sense amplifier control circuit
528
.
As shown in
FIG. 16
, sense amplifier control circuit
528
includes a level conversion circuit
572
receiving and inverting signal XBLATL for level conversion, a buffer circuit
574
receiving a signal output from level conversion circuit
572
and outputting a bit line equalization signal BLEQR#3, a level conversion circuit
576
receiving and converting signal XBLATL in level, and a buffer circuit
578
receiving a signal output from level conversion circuit
576
and outputting a bit line isolation signal BLIL#3. Although not shown, bit line equalization signal BLEQE#3 and bit line isolation signal BLIL#3 are transmitted to sense amplifier band SAB#3 arranged between memory cell arrays MA#2 and MA#3.
Sense amplifier control circuit
52

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