Semiconductor memory device with plural latches for read out

Details Semiconductor memory device with plural latches for read out Semiconductor memory device with plural latches for read out

1985-02-20

1987-12-22

Moffitt, James W.

Static information storage and retrieval

Addressing

Sequential

365189, 365230, G11C 700

Patent

active

047150173

ABSTRACT:
A memory device has memory cells, first latches and second latches which latch storage data from the memory cells accessed in response to a row address signal, a read circuit for reading out the contents of the first and second latches, and a control circuit for controlling the operation of the above components. In order to increase a read rate of the memory device, the read circuit alternately reads the contents of the first latches and the second latches. While the read circuit is reading out the contents of the first latches, the second latches latch the storage data of the memory cells of the next row to be selected in response to the next address signal. While the contents of the second latches are being read out, the first latches latch the storage data of the memory cells designated by the next row address signal.

REFERENCES:
patent: 4106109 (1978-08-01), Fassbender
patent: 4388621 (1983-06-01), Komatsu et al.
patent: 4415994 (1983-11-01), Ive et al.
"Memory Applications of the MNOS," Wescon Technical Papers, presented at the Western Electronic Show and Convention in Los Angeles, CA, vol. 16, pp. 4/3-1-4/3-5, Sep. 19-22, 1972.
Mattos et al., "`Nibble-Mode'` Beschleunigt Speicherzugriff", Elektronik, vol. 31, No. 15 pp. 27-30, Jul. 1982.
Patent Abstracts of Japan, vol. 2, No. 127, Oct. 25, 1978, p. 7626 E 78; & JP-A-53 94 140 (Hitachi Seisakusho K.K.) 08-17-1978.

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