Semiconductor memory device with multiple registers enabling ser

Details Semiconductor memory device with multiple registers enabling ser Semiconductor memory device with multiple registers enabling ser

1993-08-24

1995-02-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sequential

36518912, 365219, G11C 700

Patent

active

053922549

ABSTRACT:
A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a" units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.

REFERENCES:
patent: 4644502 (1987-02-01), Kawashima
patent: 4855959 (1989-08-01), Kobayashi

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