Semiconductor memory device with MOS transistors each having...

Details Semiconductor memory device with MOS transistors each having... Semiconductor memory device with MOS transistors each having...

2007-06-19

2007-06-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185290

Reexamination Certificate

active

11248425

ABSTRACT:
A semiconductor memory device includes a memory cell array, word lines, select gate lines, and switch elements. The memory cell array includes a plurality of memory cells arranged in a matrix. Each of the memory cells includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor which has a drain connected to a source of the first MOS transistor. Each of the word lines connects commonly the control gates of the first MOS transistors in a same row. Each of the select gate lines connects commonly the gates of the second MOS transistors in a same row. The switch elements, in an erase operation, electrically connect the select gate lines to a semiconductor substrate in which the memory cell array is formed.

REFERENCES:
patent: 2005/0068808 (2005-03-01), Quader et al.
Do Dormans, et al., “High-density low-voltage byte-erasable EEPROM memory based on a 2T-FNFN Flash cell”, NVSMW, Feb. 17, 2003, pp. 21, 22 and 1 cover page.
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, NVSMW 4.1, Feb. 1997, pp. 1-3.

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