Semiconductor memory device with MOS transistors each having...

Details Semiconductor memory device with MOS transistors each having... Semiconductor memory device with MOS transistors each having...

2007-06-19

2007-06-19

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S185130

Reexamination Certificate

active

11153531

ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, first metal wiring layers, and metal wiring lines. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. Each word line is formed by connecting commonly the control gates in a same row. The row decoder selects any one of the word lines. The first metal wiring layers are provided for the word lines in a one-to-one correspondence. The first metal wiring layers are electrically connected to the corresponding ones of the word lines and transmit a first row select signal for the row decoder to select one of the word lines. The metal wiring lines are formed at a plurality of levels. The first metal wiring layers are made of the metal wiring lines located at the level of the lowest layer.

REFERENCES:
patent: 6570214 (2003-05-01), Wu
patent: 6853029 (2005-02-01), Ichige et al.
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications” Non-Volatile Semiconductor Memory Workshop 4.1, Feb. 1997, pp. 1-3.

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