Semiconductor memory device with MOS transistors, each...

Details Semiconductor memory device with MOS transistors, each... Semiconductor memory device with MOS transistors, each...

2007-02-20

2007-02-20

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185180, C365S185230

Reexamination Certificate

active

11087760

ABSTRACT:
A semiconductor memory device comprises memory cells, and bit lines. The each of the memory cells has a first MOS transistor and a second MOS transistor. The first MOS transistor includes a floating gate and a control gate. The second MOS transistor has a drain connected to the source of a first MOS transistor. The bit lines connect electrically to drains of the first MOS transistors. In a write operation, a write inhibit voltage settable to a negative voltage is applied to the bit lines unconnected to a selected memory cell in a write operation.

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Ton Ditewig, et al., “An Embedded 1.2V-Read Flash Memory Module in a 0.18μm Logic Process.”, IEEE, ISSCC, Session 2, Non-Volatile Memories, Digest of Technical Papers, Salon-1-6, Feb. 5, 2001, 3 pages.
Kenichi Imamiya, et al., “A 125-mm21-Gb NAND Flash Memory With 10-MByte/s Program Speed”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1493-1501.
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, Non-Volatile Semiconductor Memory Workshop 4.1, 1997, pp. 1-3.

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