Semiconductor memory device with MOS transistors, each...

Details Semiconductor memory device with MOS transistors, each... Semiconductor memory device with MOS transistors, each...

2007-07-17

2007-07-17

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185130, C365S185170

Reexamination Certificate

active

11111878

ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

REFERENCES:
patent: 6353242 (2002-03-01), Watanabe et al.
patent: 6512253 (2003-01-01), Watanabe et al.
patent: 7064978 (2006-06-01), Lee et al.
patent: 2004/0240273 (2004-12-01), Sakui
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, Non-Volatile Semiconductor Memory Workshop 4.1, 1997, pp. 1-3.
Ton Ditewig, et al., “An Embedded 1.2V-Read Flash Memory Module in a 0.18μm Logic Process”, Solid-State Circuits Conference, Digest of Technical Papers ISSCC, Feb. 5-7, 2001, pp. 34-35 and 425.

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